參數(shù)資料
型號(hào)： MT48LC8M8A2TG-8EL:GIT
元件分類： DRAM
英文描述： 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝： 0.400 INCH, PLASTIC, TSOP2-54
文件頁(yè)數(shù)： 20/55頁(yè)
文件大?。?/td> 1454K
27
64Mb: x4, x8, x16 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM.pmd – Rev. H; Pub. 12/04
2002 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16
SDRAM
TRUTH TABLE 2 – CKE
(Notes: 1-4)
CKEn-1 CKEn
CURRENT STATE
COMMANDn
ACTIONn
NOTES
L
Power-Down
X
Maintain Power-Down
Self Refresh
X
Maintain Self Refresh
Clock Suspend
X
Maintain Clock Suspend
L
H
Power-Down
COMMAND INHIBIT or NOP
Exit Power-Down
5
Self Refresh
COMMAND INHIBIT or NOP
Exit Self Refresh
6
Clock Suspend
X
Exit Clock Suspend
7
H
L
All Banks Idle
COMMAND INHIBIT or NOP
Power-Down Entry
All Banks Idle
AUTO REFRESH
Self Refresh Entry
Reading or Writing
VALID
Clock Suspend Entry
H
See Truth Table 3
NOTE:
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided
that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT
or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP
commands must be provided during tXSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock
edge n + 1.
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