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參數(shù)資料
| 型號： | MT47H64M16HQ-3IT:G |
| 元件分類： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.4 ns, PBGA60 |
| 封裝： | ROHS COMPLAINT, PLASTIC, FBGA-60 |
| 文件頁數(shù)： | 95/135頁 |
| 文件大?。?/td> | 9307K |
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2. tDS nominal slew rate for a rising signal is defined as the slew rate between the last
crossing of Vref(DC) and the first crossing of Vih(AC) MIN. tDS nominal slew rate for a
falling signal is defined as the slew rate between the last crossing of Vref(DC) and the
first crossing of Vil(AC) MAX. If the actual signal is always earlier than the nominal slew
rate line between the shaded “Vref(DC) to AC region,” use the nominal slew rate for
the derating value (see Figure 26 (page 66)). If the actual signal is later than the nomi-
nal slew rate line anywhere between the shaded “Vref(DC) to AC region,” the slew rate
of a tangent line to the actual signal from the AC level to DC level is used for the derat-
ing value (see Figure 27 (page 66)).
3. tDH nominal slew rate for a rising signal is defined as the slew rate between the last
crossing of Vil(DC) MAX and the first crossing of Vref(DC). tDH nominal slew rate for a
falling signal is defined as the slew rate between the last crossing of Vih(DC) MIN and
the first crossing of Vref(DC). If the actual signal is always later than the nominal slew
rate line between the shaded “DC level to Vref(DC) region,” use the nominal slew rate
for the derating value (see Figure 28 (page 67)). If the actual signal is earlier than the
nominal slew rate line anywhere between shaded “DC to Vref(DC) region,” the slew
rate of a tangent line to the actual signal from the DC level to Vref(DC) level is used for
the derating value (see Figure 29 (page 67)).
4. Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached Vih[AC]/Vil[AC] at the time of the rising clock transition), a valid
input signal is still required to complete the transition and reach Vih(AC)/Vil(AC).
5. For slew rates between the values listed in this table, the derating values may be ob-
tained by linear interpolation.
6. These values are typically not subject to production test. They are verified by design and
characterization.
7. Single-ended DQS requires special derating. The values in Table 32 (page 64) are the
DQS single-ended slew rate derating with DQS referenced at Vref and DQ referenced at
the logic levels tDSb and tDHb. Converting the derated base values from DQ referenced
to the AC/DC trip points to DQ referenced to Vref is listed in Table 34 (page 65) and
Table 35 (page 65). Table 34 (page 65) provides the Vref-based fully derated values
fully derated values for the DQ (tDSa and tDHa) for DDR2-400.
1Gb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
PDF: 09005aef821ae8bf
Rev. P 1/09 EN
62
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H64M16HQ-3L | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
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