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參數資料
| 型號： | MSC8101M1375C |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | Network Digital Signal Processor |
| 中文描述： | 64-BIT, 68.75 MHz, OTHER DSP, PBGA332 |
| 封裝： | 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332 |
| 文件頁數： | 99/104頁 |
| 文件大?。?/td> | 877K |
| 代理商： | MSC8101M1375C |
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Layout Practices
MSC8101 Technical Data, Rev. 16
Freescale Semiconductor
4-3
Since the address pins switch once at every second cycle, the address pins frequency is a quarter of the bus
frequency (that is, 25 MHz).
For the same reason the data pins frequency is 3.125 MHz.
Calculating internal power (from
Table 2-5
values):
P
CORE
(200) = ((P
CORE
– P
LCO
)/300)
×
200 + P
LCO
=((450 – 3) / 300
×
200 + 3 = 301
P
CPM
(100) = ((P
CPM
– P
LCP
) / 200)
×
100 + P
LCP
= ((320 – 6) / 200)
×
100 + 6 = 163
P
SIU
(50) = ((P
SIU
– P
LSI
) / 100)
×
50 + P
LSI
= ((80 – 2) / 100)
×
50 + 2 = 41
P
INT
= P
CORE
(200) + P
CPM
(100) + P
SIU
(50) = 301 + 163 + 41 = 505
P
D
= P
INT
+ P
I/O
= 505 + 67 = 572
Maximum allowed ambient temperature is:
T
A
= T
J
– (PD
× θ
JA
)
4.4 Layout Practices
Each
V
CC
and
V
DD
pin on the MSC8101 should be provided with a low-impedance path to the board’s power supply.
Similarly, each
GND
pin should be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on the chip. The
V
CC
power supply should be bypassed to ground using at least four 0.1 μF
by-pass capacitors located as closely as possible to the four sides of the package. The capacitor leads and
associated printed circuit traces connecting to chip
V
CC
,
V
DD
, and
GND
should be kept to less than half an inch per
capacitor lead. A four-layer board is recommended, employing two inner layers as
V
CC
and
GND
planes.
All output pins on the MSC8101 have fast rise and fall times. Printed circuit board (PCB) trace interconnection
length should be minimized in order to minimize undershoot and reflections caused by these fast output switching
times. This recommendation particularly applies to the address and data busses. Maximum PCB trace lengths of six
inches are recommended. Capacitance calculations should consider all device loads as well as parasitic
capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes especially critical in
systems with higher capacitive loads because these loads create higher transient currents in the
V
CC
,
V
DD
, and
GND
circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to
minimize the noise levels on the PLL supply pins.
There are 2 pairs of PLL supply pins:
V
CCSYN
-
GND
SYN
and
V
CCSYN1
-
GND
SYN1
. Each pair supplies one PLL. To
ensure internal clock stability, filter the power to the
V
CCSYN
and
V
CCSYN1
inputs with a circuit similar to the one in
Figure 0-1.
. To filter as much noise as possible, place the circuit as close as possible to
V
CCSYN
and
V
CCSYN1
. The
0.01-μF capacitor should be closest to
V
CCSYN
and
V
CCSYN1
, followed by the 10-μF capacitor, the 10-nH inductor,
and finally the 10-
resistor to
V
DD
. These traces should be kept short and direct.
Table 4-1.
Power Dissipation
Pins
Number of Pins
Switching
×
C
×
V
DDH2
×
f
×
10
–3
Power in mW
Address
Data, HRD, HRW
CLKOUT
4
34
1
×
30
×
30
×
30
×
3.3
2
×
3.3
2
×
3.3
2
×
12.5
×
10
–3
×
3. 125
×
10
–3
×
50
×
10
–3
16.25
34.75
16
Total P
I/O
67
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