參數(shù)資料
型號: MSC8101M1375C
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: Network Digital Signal Processor
中文描述: 64-BIT, 68.75 MHz, OTHER DSP, PBGA332
封裝: 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332
文件頁數(shù): 97/104頁
文件大小: 877K
代理商: MSC8101M1375C
MSC8101 Technical Data, Rev. 16
Freescale Semiconductor
4-1
Design Considerations
4
This chapter includes design and layout guidelines for manufacturing boards using the MSC8102.
4.1 Thermal Design Considerations
The average chip-junction temperature
,
T
J
,
in
°
C can be obtained from the following:
T
J
= T
A
+ (P
D
θ
JA
)
Equation 1
where
T
A
= ambient temperature
°
C
θ
JA
= package thermal resistance
,
junction to ambient
,
°
C/W
P
D
= P
INT
+ P
I/O
in W
P
INT
= I
DD
×
V
DD
in W—chip internal power
P
I/O
= power dissipation on output pins in W—user determined
The user should set T
A
and P
D
such that T
J
does not exceed the maximum operating conditions. In case T
J
is too
high, the user should either lower the ambient temperature or the power dissipation of the chip.
4.2 Electrical Design Considerations
The input voltage must not exceed the I/O supply
V
DDH
by more than 2.5 V at any time, including during power-on
reset. In turn,
V
DDH
can exceed
V
DD
/
V
CCSYN
by more than 3.3 V during power-on reset, but for no more than 100 ms.
V
DDH
should not exceed
V
DD
/
V
CCSYN
by more than 2.1 V during normal operation.
V
DD
/
V
CCSYN
must not exceed
V
DDH
by more than 0.4 V at any time, including during power-on reset. Therefore the recommendation is to use
“bootstrap” diodes between the power rails, as shown in
Figure 4-1
.
Figure 4-1.
Bootstrap Diodes for Power-Up Sequencing
I/O Power
Core/PLL
Supply
MUR420
MUR420
MUR420
MUR420
3.3 V (V
DDH
)
1.6 V (V
DD
/V
CCSYN
)
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