參數(shù)資料
型號(hào): MSC8101M1375C
廠商: MOTOROLA INC
元件分類(lèi): 數(shù)字信號(hào)處理
英文描述: Network Digital Signal Processor
中文描述: 64-BIT, 68.75 MHz, OTHER DSP, PBGA332
封裝: 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332
文件頁(yè)數(shù): 63/104頁(yè)
文件大?。?/td> 877K
代理商: MSC8101M1375C
AC Timings
MSC8101 Technical Data, Rev. 16
Freescale Semiconductor
2-23
Note:
The timing values refer to minimum system timing requirements. Actual implementation requires
conformance to the specific protocol requirements. Refer to
Chapter 1
to identify the specific input and
output signals associated with the referenced internal controllers and supported communication protocols.
For example, FCC1 supports ATM/Utopia operation in slave mode, multi-PHY master direct polling
mode, and multi-PHY master multiplexed polling mode and each of these modes supports its own set of
signals; the direction (input or output) of some of the shared signal names depends on the selected mode.
2.6.7
JTAG Signals
Figure 2-19.
PIO, Timer, and DMA Signal Diagram
Table 2-22.
JTAG Timing
No.
Characteristics
All frequencies
Unit
Min
Max
500
TCK frequency of operation
0.0
40.0
MHz
501
TCK cycle time
25.0
ns
502
TCK clock pulse width measured at 1.6 V
12.5
ns
503
TCK rise and fall times
0.0
3.0
ns
508
TMS, TDI data set-up time
6.0
ns
509
TMS, TDI data hold time
3.0
ns
510
TCK low to TDO data valid
0.0
15.0
ns
511
TCK low to TDO high impedance
0.0
20.0
ns
512
TRST assert time
100.0
ns
513
TRST set-up time to TCK low
40.0
ns
Figure 2-20.
Test Clock Input Timing Diagram
DLLIN
PIO/TIMER/DMA inputs
PIO/TIMER/DMA outputs
22
23
42
TCK
(Input)
V
M
V
M
V
IH
V
IL
501
502
502
503
503
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