參數(shù)資料
型號(hào)： MSC8101M1375C
廠商： MOTOROLA INC
元件分類： 數(shù)字信號(hào)處理
英文描述： Network Digital Signal Processor
中文描述： 64-BIT, 68.75 MHz, OTHER DSP, PBGA332
封裝： 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332
文件頁數(shù)： 11/104頁
文件大小： 877K
代理商： MSC8101M1375C
System Bus, HDI16, and Interrupt Signals
MSC8101 Technical Data, Rev. 16
Freescale Semiconductor
1-7
Although there are eight interrupt request (
IRQ
) connections to the core processor, there are multiple external lines
that can connect to these internal signal lines. After reset, the default configuration includes two
IRQ1
and two
IRQ7
input lines. The designer must select one line for each required interrupt and reconfigure the other external signal
line or lines for alternate functions.
Table 1-5.
System Bus, HDI16, and Interrupt Signals
Signal
Data Flow
Description
A[0–31]
Input/Output
Address Bus
When the MSC8101 is in external master bus mode, these pins function as the address bus. The
MSC8101 drives the address of its internal bus masters and responds to addresses generated by
external bus masters. When the MSC8101 is in Internal Master Bus mode, these pins are used as
address lines connected to memory devices and are controlled by the MSC8101 memory controller.
TT[0–4]
Input/Output
Bus Transfer Type
The bus master drives these pins during the address tenure to specify the type of transaction.
TSIZ[0–3]
Input/Output
Transfer Size
The bus master drives these pins with a value indicating the number of bytes transferred in the
current transaction.
TBST
Input/Output
Bus Transfer Burst
The bus master asserts this pin to indicate that the current transaction is a burst transaction
(transfers four quad words).
IRQ1
GBL
Input
Input/Output
Interrupt Request 1
1
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
Global
1
When a master within the chip initiates a bus transaction, it drives this pin. When an external master
initiates a bus transaction, it should drive this pin. Assertion of this pin indicates that the transfer is
global and it should be snooped by caches in the system.
Reserved
BADDR29
IRQ2
Output
Output
Input
The primary configuration is reserved.
Burst Address 29
1
One of five outputs of the memory controller. These pins connect directly to memory devices
controlled by the MSC8101 memory controller.
Interrupt Request 2
1
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
Reserved
BADDR30
IRQ3
Output
Output
Input
The primary configuration is reserved.
Burst Address 30
1
One of five outputs of the memory controller. These pins connect directly to memory devices
controlled by the MSC8101 memory controller.
Interrupt Request 3
1
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
Reserved
BADDR31
IRQ5
Output
Output
Input
The primary configuration is reserved.
Burst Address 31
1
One of five outputs of the memory controller. These pins connect directly to memory devices
controlled by the MSC8101 memory controller.
Interrupt Request 5
1
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
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