參數(shù)資料
型號(hào): MSC8101M1375C
廠商: MOTOROLA INC
元件分類: 數(shù)字信號(hào)處理
英文描述: Network Digital Signal Processor
中文描述: 64-BIT, 68.75 MHz, OTHER DSP, PBGA332
封裝: 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332
文件頁數(shù): 47/104頁
文件大?。?/td> 877K
代理商: MSC8101M1375C
AC Timings
MSC8101 Technical Data, Rev. 16
Freescale Semiconductor
2-7
2.6 AC Timings
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and
inputs. AC timings are based on a 50 pF load, except where noted otherwise, and 50
transmission line.
2.6.1
Output Buffer Impedances
2.6.2
Clocking and Timing Characteristics
Table 2-9.
Output Buffer Impedances
Output Buffers
Typical Impedance (
)
System Bus
35
Memory Controller
35
Parallel I/O
55
Note:
These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.
Table 2-10.
System Clock Parameters
Characteristic
Minimum
Maximum
Unit
Phase Jitter between BCLK and DLLIN
0.5
ns
CLKIN frequency
1,2
18
75
MHz
CLKIN slope
5
ns
DLLIN slope
2
ns
CLKOUT frequency jitter
(0.01/CLKOUT) + CLKIN jitter
ns
Delay between CLKOUT and DLLIN
5
ns
Notes:
1.
Low CLKIN frequency causes poor PLL performance. Choose a CLKIN frequency high enough to keep the frequency after the
predivider (SPLLMFCLK) higher than 18 MHz.
CLKIN should have a 50%
±
5% duty cycle.
2.
Table 2-11.
Clock Ranges
Clock
Symbol
Maximum Rated Core Frequency
All
Max. Values for SC140 Clock Rating of:
Min
250 MHz
275 MHz
300 MHz
Input Clock
CLKIN
18 MHz
83.3
91.67 MHz
100 MHz
SPLL MF Clock
SPLLMFCLK
18 MHz
31.25
34.38 MHz
37.5 MHz
Bus/Output
BCLK
CLKOUT
18 MHz
83.3 MHz
91.67 MHz
100 MHz
Serial Communications Controller
SCLK
35 MHz
83.3 MHz
91.67 MHz
100 MHz
Communications Processor Module
CPMCLK
70 MHz
166.7 MHz
183.3 MHz
200 MHz
SC140 Core
DSPCLK
72 MHz
250 MHz
275 MHz
300 MHz
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