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| 型號： | MSC8101M1375C |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Network Digital Signal Processor |
| 中文描述： | 64-BIT, 68.75 MHz, OTHER DSP, PBGA332 |
| 封裝： | 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332 |
| 文件頁數(shù)： | 38/104頁 |
| 文件大小： | 877K |
| 代理商： | MSC8101M1375C |
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MSC8101 Technical Data, Rev. 16
1-34
Freescale Semiconductor
Signals/Connections
PD19
FCC1: TXADDR4
UTOPIA master
FCC1: TXADDR4
UTOPIA slave
FCC1: TXCLAV3
UTOPIA multi-PHY master, direct
polling
BRG1O
SPI: SPISEL
Output
Input
Input
Output
Input
FCC1: Multi-PHY Master Transmit Address Bit 4 Multiplexed Polling
This is master transmit address bit 4.
FCC1: UTOPIA Slave Transmit Address Bit 4
This is slave transmit address bit 4.
FCC1: UTOPIA Multi-PHY master Transmit Cell Available 3 Direct
Polling
Asserted by an external UTOPIA slave PHY to indicate that it can accept
one complete ATM cell.
Baud Rate Generator 1 Output
The CPM supports up to 8 BRGs for use internally by the bank-of-clocks
selection logic and/or to provide an output to one of the 8 BRG pins.
BRG1O can be the internal input to the SIU timers. When CLK5 is
selected (see PC27 above), it is the source for BRG1O which is the
default input for the SIU timers. See the system interface unit (SIU)
chapter in the
MSC8101 Reference Manual
for additional information. If
CLK5 is not enabled, BRG1O uses an internal input. If TMCLK is
enabled (see PC26 above), the BRG1O input to the SIU timers is
disabled.
SPI: Select
The SPI interface comprises four signals: master out slave in
(SPIMOSI), master in slave out (SPIMISO), clock (SPICLK) and select
(SPISEL).
The SPI can be configured as a slave or master in single- or
multiple-master environments. SPISEL is
the enable input to the SPI
slave. In a multimaster environment,
SPISEL (always an input) detects
an error when more than one master is operating. SPI masters must
output a slave select signal to enable SPI slave devices by using a
separate general-purpose I/O signal. Assertion of an SPI SPISEL while
it is master causes an error.
PD18
FCC1: RXADDR4
UTOPIA master
FCC1: RXADDR4
UTOPIA slave
FCC1: RXCLAV3
UTOPIA multi-PHY master, direct
polling
SPI: SPICLK
Output
Input
Input
Input/ Output
FCC1: UTOPIA Master Receive Address Bit 4
This is master receive address bit 4.
FCC1: UTOPIA Slave Receive Address Bit 4
This is slave receive address bit 4.
FCC1: UTOPIA Multi-PHY Master Receive Cell Available 3 Direct
Polling
Asserted by an external PHY when one complete ATM cell is available
for transfer.
SPI: Clock
The SPI interface comprises four signals: master out slave in
(SPIMOSI), master in slave out (SPIMISO), clock (SPICLK) and select
(SPISEL). The SPI can be configured as a slave or master in single- or
multiple-master environments. SPICLK is a gated clock, active only
during data transfers. Four combinations of SPICLK phase and polarity
can be configured. When the SPI is a master, SPICLK is the clock
output signal that shifts received data in from SPIMISO and transmitted
data out to SPIMOSI.
Table 1-10.
Port D Signals (Continued)
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose I/O
Peripheral Controller:
Dedicated I/O
Protocol
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSC8101M1375F | 功能描述:DSP 16BIT 275MHZ CPM 332-FCPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| MSC8101M1500F | 功能描述:DSP 16BIT 300MHZ CPM 332-FCPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| MSC8101UG/D | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor |
| MSC8101VT1250F | 功能描述:IC DSP 16BIT 250MHZ 332-FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| MSC8101VT1375F | 功能描述:IC DSP 16BIT 250MHZ 332-FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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