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參數(shù)資料
| 型號(hào)： | MC68HC08KH12A |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Microcontrollers |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 95/178頁(yè) |
| 文件大小： | 925K |
| 代理商： | MC68HC08KH12A |
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I/O Register Description of the Embedded Device Function
MC68HC08KH12A Data Sheet, Rev. 1.1
Freescale Semiconductor
95
9.5.1 USB Embedded Device Address Register (DADDR)
DEVEN — Enable USB Embedded Device
These bit enable or disable the embedded device function. It is used together with PEN1-PEN4 to
control the enumeration sequence. Reset clears these bits.
1 = USB Embedded Device enabled
0 = USB Embedded Device disabled
DADD6-DADD0 — USB Embedded Device Function Address
These bits specify the address of the embedded device function. Reset clears these bits.
9.5.2 USB Embedded Device Interrupt Register 0 (DIR0)
TXD0F — Embedded Device Endpoint 0 Data Transmit Flag
This read only bit is set after the data stored in embedded device Endpoint 0 transmit buffers has been
sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the
transmit buffers, software must clear this flag by writing a logic 1 to the TXD0FR bit. To enable the next
data packet transmission, TX0E must also be set. If TXD0F bit is not cleared, a NAK handshake will
be returned in the next IN transaction. Reset clears this bit. Writing to TXD0F has no effect.
1 = Transmit on embedded device Endpoint 0 has occurred
0 = Transmit on embedded device Endpoint 0 has not occurred
RXD0F — Embedded Device Endpoint 0 Data Receive Flag
This read only bit is set after the USB embedded device module has received a data packet and
responded with an ACK handshake packet. Software must clear this flag by writing a logic 1 to the
RXD0FR bit after all of the received data has been read. Software must also set RX0E bit to one to
enable the next data packet reception. If RXD0F bit is not cleared, a NAK handshake will be returned
in the next OUT transaction.
Reset clears this bit. Writing to RXD0F has no effect.
1 = Receive on embedded device Endpoint 0 has occurred
0 = Receive on embedded device Endpoint 0 has not occurred
Address: $0048
Bit 7
6
5
4
3
2
1
Bit 0
Read:
DEVEN
DADD6
DADD5
DADD4
DADD3
DADD2
DADD1
DADD0
Write:
Reset:
0
0
0
0
0
0
0
0
Figure 9-16. USB Embedded Device Address Register (DADDR)
Address: $0049
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TXD0F
RXD0F
0
0
TXD0IE
RXD0IE
0
0
Write:
TXD0FR
RXD0FR
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-17. USB Embedded Device Interrupt Register 0 (DIR0)
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