參數(shù)資料
型號: MC68HC08KH12A
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Microcontrollers
中文描述: 微控制器
文件頁數(shù): 67/178頁
文件大?。?/td> 925K
代理商: MC68HC08KH12A
Functional Description
MC68HC08KH12A Data Sheet, Rev. 1.1
Freescale Semiconductor
67
8.3.6 Programming the PLL
The following procedure shows how to program the PLL.
1.
Choose the desired bus frequency, f
BUS
.
The relationship between the VCO frequency f
VCLK
and the bus frequency f
BUS
is
2P
The VCO frequency need to be at 48MHz for the USB module reference clock.
Choose P = 0, 1, 2, or 3 for a bus frequency of 12MHz, 6MHz, 3MHz, or 1.5MHz respectively.
2.
Choose a practical PLL (crystal) reference frequency, f
RCLK
, and the reference clock divider, R.
Frequency errors to the PLL are corrected at a rate of f
RCLK
/R. For stability and lock time reduction,
this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate.
The relationship between the VCO frequency f
VCLK
and the reference frequency f
RCLK
is
Choose the reference divider R = 1 for fast lock. Choose a f
RCLK
frequency with an integer divisor
of f
BUS
and solve for N.
3.
Program the PLL registers accordingly:
a.
In the PRE bits of the PLL control register (PCTL), program the binary equivalent of P.
b.
In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high
(PMSH), program the binary equivalent of N.
c.
In the PLL reference divider select register (PRDS), program the binary coded equivalent of
R.
Table 8-1
provides a numeric example (numbers are in hexadecimal notation):
Table 8-1. CGM Numeric Example
f
BUS
f
RCLK
P
N
R
6MHz
6MHz
1
004
1
fVCLK
4
fBUS
×
=
2P
48MHz
4
fBUS
×
=
fVCLK
2P
-------R
×
(
)
=
hence: 48MHz
2P
-------R
×
(
)
=
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