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參數(shù)資料
| 型號(hào)： | MC68HC08KH12A |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Microcontrollers |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 151/178頁(yè) |
| 文件大?。?/td> | 925K |
| 代理商： | MC68HC08KH12A |
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Port-D Keyboard Interrupt Block Diagram
MC68HC08KH12A Data Sheet, Rev. 1.1
Freescale Semiconductor
151
15.3.1 Port-D Keyboard Interrupt Functional Description
Writing to the KBDIE7–KBDIE0 bits in the keyboard interrupt enable register independently enables or
disables each port D pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin in port-D also
enables its internal pullup device. A logic 0 applied to an enabled keyboard interrupt pin latches a
keyboard interrupt request.
A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODED
bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt.
If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an
interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on
one pin because another pin is still low, software can disable the latter pin while it is low.
If the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as
long as any keyboard pin is low.
If the MODED bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both
of the following actions must occur to clear a keyboard interrupt request:
Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1
to the ACKD bit in the keyboard status and control register KBDSCR. The ACKD bit is useful in
applications that poll the keyboard interrupt pins and require software to clear the keyboard
interrupt request. Writing to the ACKD bit prior to leaving an interrupt service routine can also
prevent spurious interrupts due to noise. Setting ACKD does not affect subsequent transitions on
the keyboard interrupt pins. A falling edge that occurs after writing to the ACKD bit latches another
interrupt request. If the keyboard interrupt mask bit, IMASKD, is clear, the CPU loads the program
counter with the vector address at locations $FFEA and $FFEB.
Return of all enabled keyboard interrupt pins to logic 1 — As long as any enabled keyboard
interrupt pin is at logic 0, the keyboard interrupt remains set.
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur
in any order.
If the MODED bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODED clear, a
vector fetch or software clear immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODED bit, clearing the interrupt request even if a
keyboard interrupt pin stays at logic 0.
The keyboard flag bit (KEYDF) in the keyboard status and control register can be used to see if a pending
interrupt exists. The KEYDF bit is not affected by the keyboard interrupt mask bit (IMASKD) which makes
it useful in applications where polling is preferred.
To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the
pin as an input and read the data register.
NOTE
Setting a keyboard interrupt enable bit (KBDIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction register.
However, the data direction register bit must be a logic 0 for software to
read the pin.
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