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參數(shù)資料
| 型號： | MC68HC08KH12A |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Microcontrollers |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 147/178頁 |
| 文件大?。?/td> | 925K |
| 代理商： | MC68HC08KH12A |
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IRQ Module During Break Interrupts
MC68HC08KH12A Data Sheet, Rev. 1.1
Freescale Semiconductor
147
14.3.1 IRQ1 Pin
A logic zero on the IRQ1 pin can latch an interrupt request into the IRQ1 latch. A vector fetch, software
clear, or reset clears the IRQ1 latch.
If the MODE1 bit is set, the IRQ1 pin is both falling-edge-sensitive and low-level-sensitive. With MODE1
set, both of the following actions must occur to clear IRQ1:
Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the latch. Software may generate the interrupt acknowledge signal by writing a logic one to the
ACK1 bit in the interrupt status and control register (ISCR). The ACK1 bit is useful in applications
that poll the IRQ1 pin and require software to clear the IRQ1 latch. Writing to the ACK1 bit prior to
leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK1
does not affect subsequent transitions on the IRQ1 pin. A falling edge that occurs after writing to
the ACK1 bit latches another interrupt request. If the IRQ1 mask bit, IMASK1, is clear, the CPU
loads the program counter with the vector address at locations $FFFA and $FFFB.
Return of the IRQ1 pin to logic one — As long as the IRQ1 pin is at logic zero, IRQ1 remains active.
The vector fetch or software clear and the return of the IRQ1 pin to logic one may occur in any order. The
interrupt request remains pending as long as the IRQ1 pin is at logic zero. A reset will clear the latch and
the MODE1 control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE1 bit is clear, the IRQ1 pin is falling-edge-sensitive only. With MODE1 clear, a vector fetch or
software clear immediately clears the IRQ1 latch.
The IRQF1 bit in the ISCR register can be used to check for pending interrupts. The IRQF1 bit is not
affected by the IMASK1 bit, which makes it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ1 pin.
NOTE
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
14.4 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ1 latch can be cleared during the break
state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during
the break state. (See
Chapter 7 System Integration Module (SIM)
.)
To allow software to clear the IRQ1 latch during a break interrupt, write a logic one to the BCFE bit. If a
latch is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the latches during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero
(its default state), writing to the ACK1 bit in the IRQ status and control register during the break state has
no effect on the IRQ latch.
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