CGM Registers
MC68HC08KH12A Data Sheet, Rev. 1.1
Freescale Semiconductor
73
PRE1 and PRE0 — Prescaler program bits
These read/write bits control a prescaler that selects the prescaler power-of-two multiplier P. (See
8.3.3 PLL Circuits
and
8.3.6 Programming the PLL
.) PRE1:PRE0 cannot be written when the PLLON
bit is set. Reset clears these bits.
Table 8-2. PRE[1:0] Programming
8.5.2 PLL
Bandwidth Control Register (PBWC)
The PLL bandwidth control register:
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control. Since this CGM is optimized a
frequency output of 48MHz for the USB module, automatic control should be set. Reset clears the
AUTO bit.
1 = Automatic bandwidth control (recommended)
0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK,
is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic
zero and has no meaning. The write one function of this bit is reserved for test, so this bit must
always
be written a zero. Reset clears the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
ACQ — Acquisition Mode Bit
When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode
or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is
in acquisition or tracking mode.
PRE1
PRE0
P
Prescaler Multiplier
0
0
0
1
0
1
1
2
1
0
2
4
1
1
3
8
Address:
$003B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AUTO
LOCK
ACQ
0
0
0
0
0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-5. PLL Bandwidth Control Register (PBWC)