Functional Description
MC68HC08KH12A Data Sheet, Rev. 1.1
Freescale Semiconductor
113
11.4.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs or the TIM clock pin, PTE0/TCLK. The
prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in
the TIM status and control register (TSC) select the TIM clock source.
11.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter
into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input
captures can generate TIM CPU interrupt requests.
11.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU
interrupt requests.
$0015
TIM Counter Modulo Register
Low
(TMODL)
Read:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Write:
Reset:
1
1
1
1
1
1
1
1
$0016
TIM Channel 0 Status and Con-
trol Register
(TSC0)
Read:
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
Write:
0
Reset:
0
0
0
0
0
0
0
0
$0017
TIM Channel 0
Register High
(TCH0H)
Read:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Write:
Reset:
X
X
X
X
X
X
X
X
$0018
TIM Channel 0
Register Low
(TCH0L)
Read:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Write:
Reset:
X
X
X
X
X
X
X
X
$0019
TIM Channel 1 Status and Con-
trol Register
(TSC1)
Read:
CH1F
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
Write:
0
Reset:
0
0
0
0
0
0
0
0
$001A
TIM Channel 1
Register High
(TCH1H)
Read:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Write:
Reset:
X
X
X
X
X
X
X
X
$001B
TIM Channel 1
Register Low
(TCH1L)
Read:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Write:
Reset:
X
X
X
X
X
X
X
X
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented
X = Indeterminate
Figure 11-2. TIM I/O Register Summary (Continued)