參數(shù)資料
型號： MC68HC08KH12A
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： Microcontrollers
中文描述： 微控制器
文件頁數(shù)： 51/178頁
文件大?。?/td> 925K
代理商： MC68HC08KH12A
SIM Counter
MC68HC08KH12A Data Sheet, Rev. 1.1
Freescale Semiconductor
51
Reset can wake a device from the suspended mode. A device may take up to 10 ms to wake up from the
suspended state.
7.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescalar for the computer operating properly module (COP). The SIM counter uses 12 stages for
counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP
module. The SIM counter is clocked by the falling edge of CGMXCLK.
7.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock
state machine.
7.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a logic one, then the stop recovery is reduced from the normal delay
of 4096 CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned
oscillators that do not require long start-up times from stop mode. External crystal applications should use
the full stop recovery time, that is, with SSREC cleared in the configuration register (CONFIG).
7.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (
See 7.6.2 Stop Mode
for details.) The SIM counter is
free-running after all reset states. (
See 7.3.2 Active Resets from Internal Sources
for counter control and
internal reset recovery sequences.)
7.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
Interrupts
–
Maskable hardware CPU interrupts
–
Non-maskable software interrupt instruction (SWI)
Reset
Break interrupts
7.5.1 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event.
Figure 7-8
flow charts the handling of system interrupts.
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared).
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