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參數(shù)資料
| 型號(hào)： | MC68HC08KH12A |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Microcontrollers |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 68/178頁 |
| 文件大小： | 925K |
| 代理商： | MC68HC08KH12A |
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Clock Generator Module (CGM)
MC68HC08KH12A Data Sheet, Rev. 1.1
68
Freescale Semiconductor
8.3.7 Special Programming Exceptions
The programming method described in
8.3.6 Programming the PLL
does not account for three possible
exceptions. A value of zero for R, N, or L is meaningless when used in the equations given. To account
for these exceptions:
A zero value for R or N is interpreted exactly the same as a value of one. A zero value for L disables the
PLL and prevents its selection as the source for the base clock. (See
8.3.8 Base Clock Selector Circuit
.)
8.3.8 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the PLL clock, CGMPCLK, as the
source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits
up to three CGMXCLK cycles and three CGMPCLK cycles to change from one clock source to the other.
During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by
two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock
frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMPCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock
cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if
the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or
deselection of the VCO clock.
This circuit is also used to select either the crystal clock, CGMXCLK or the VCO clock, CGMVCLK, as the
source of the USB clock, USBCLK.
8.3.9 CGM External Connections
In its typical configuration, the CGM requires seven external components. Five of these are for the crystal
oscillator and two are for the PLL.
The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in
Figure 8-2
.
Figure 8-2
shows only the logical representation of the internal components and may not represent actual
circuitry. The oscillator configuration uses five components:
Crystal, X
1
Fixed capacitor, C
1
Tuning capacitor, C
2
(can also be a fixed capacitor)
Feedback resistor, R
B
Series resistor, R
S
(optional)
The series resistor (R
S
) is included in the diagram to follow strict Pierce oscillator guidelines and may not
be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal
manufacturer’s data for more information.
Figure 8-2
also shows the external components for the PLL:
Bypass capacitor, C
BYP
Filter capacitor, C
F
Routing should be done with great care to minimize signal cross talk and noise.
See
Chapter 17 Electrical Specifications
for capacitor and resistor values.
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