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參數(shù)資料
| 型號(hào)： | MC68HC08KH12A |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Microcontrollers |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 66/178頁(yè) |
| 文件大小： | 925K |
| 代理商： | MC68HC08KH12A |
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Clock Generator Module (CGM)
MC68HC08KH12A Data Sheet, Rev. 1.1
66
Freescale Semiconductor
its mode, described in
8.3.4 Acquisition and Tracking Modes
. The value of the external capacitor and the
reference frequency determines the speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final
reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final
reference frequency, f
RDV
. The circuit determines the mode of the PLL and the lock condition based on
this comparison.
8.3.4 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two operating modes:
Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the
VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in
the PLL bandwidth control register. (See
8.5.2 PLL Bandwidth Control Register (PBWC)
.)
Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the
VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL
enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected
as the base clock source. (See
8.3.8 Base Clock Selector Circuit
.) The PLL is automatically in
tracking mode when not in acquisition mode or when the ACQ bit is set.
8.3.5 Manual and Automatic PLL Bandwidth Modes
This CGM is optimized for Automatic PLL Bandwidth Mode, and is the mode recommended for most
users.
In automatic bandwidth control mode (AUTO=1), the lock detector automatically switches between
acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. (See
8.5.2 PLL
Bandwidth Control Register (PBWC)
.) If PLL interrupts are enabled, the software can wait for a PLL
interrupt request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit
continuously (during PLL startup, usually) or at periodic intervals. In either case, when the LOCK bit is set,
the VCO clock is safe to use as the source for the base clock. (See
8.3.8 Base Clock Selector Circuit
.) If
the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a
severe noise hit and the software must take appropriate action, depending on the application. (See
8.6
Interrupts
for information and precautions on using interrupts.) The following conditions apply when the
PLL is in automatic bandwidth control mode:
The ACQ bit (See
8.5.2 PLL Bandwidth Control Register (PBWC)
.) is a read-only indicator of the
mode of the filter. (See
8.3.4 Acquisition and Tracking Modes
.)
The ACQ bit is set when the VCO frequency is within a certain tolerance,
TRK
, and is cleared when
the VCO frequency is out of a certain tolerance,
UNT
. (See
8.8 Acquisition/Lock Time
Specifications
for more information.)
The LOCK bit is a read-only indicator of the locked state of the PLL.
The LOCK bit is set when the VCO frequency is within a certain tolerance,
LOCK
, and is cleared
when the VCO frequency is out of a certain tolerance
UNL
. (See
8.8 Acquisition/Lock Time
Specifications
for more information.)
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling
the LOCK bit. (See
8.5.1 PLL Control Register (PCTL)
.)
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