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| 型號(hào)： | MC68HC08GP8AMFB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 88/126頁(yè) |
| 文件大小： | 4243K |
| 代理商： | MC68HC08GP8AMFB |
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Clock Generator Module (CGM)
Data Sheet
MC68HC08GP8A
64
Clock Generator Module (CGM)
MOTOROLA
PLL control register (PCTL). (See 4.3.8 Base Clock Selector Circuit and 4.3.7
Special Programming Exceptions.) Reset initializes the register to $40 for a
default range multiply value of 64.
NOTE:
The VCO range select bits have built-in protection such that they cannot be written
when the PLL is on (PLLON = 1) and such that the VCO clock cannot be selected
as the source of the base clock (BCS = 1) if the VCO range select bits are all clear.
The PLL VCO range select register must be programmed correctly. Incorrect
programming can result in failure of the PLL to achieve lock.
4.5.6 PLL Reference Divider Select Register
NOTE:
PMDS may be called PRDS on other HC08 derivatives.
The PLL reference divider select register (PMDS) contains the programming
information for the modulo reference divider.
RDS3–RDS0 — Reference Divider Select Bits
These read/write bits control the modulo reference divider that selects the
reference division factor, R. (See 4.3.3 PLL Circuits and 4.3.6 Programming
the PLL.) RDS7–RDS0 cannot be written when the PLLON bit in the PCTL is
set. A value of $00 in the reference divider select register configures the
reference divider the same as a value of $01. (See 4.3.7 Special Programming
Exceptions.) Reset initializes the register to $01 for a default divide value of 1.
NOTE:
The reference divider select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
NOTE:
The default divide value of 1 is recommended for all applications.
PMDS7–PMDS4 — Unimplemented Bits
These bits have no function and always read as logic 0s.
4.6 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL
can generate a CPU interrupt request every time the LOCK bit changes state. The
PLLIE bit in the PLL control register (PCTL) enables CPU interrupts from the PLL.
PLLF, the interrupt flag in the PCTL, becomes set whether interrupts are enabled
Address:
$003B
Bit 7
654321
Bit 0
Read:
0000
RDS3
RDS2
RDS1
RDS0
Write:
Reset:
00000001
= Unimplemented
Figure 4-9. PLL Reference Divider Select Register (PMDS)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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