參數(shù)資料
型號: MC68HC08GP8AMFB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP44
封裝: PLASTIC, QFP-44
文件頁數(shù): 14/126頁
文件大?。?/td> 4243K
代理商: MC68HC08GP8AMFB
Low-Voltage Inhibit (LVI)
Data Sheet
MC68HC08GP8A
110
Low-Voltage Inhibit (LVI)
MOTOROLA
Figure 10-1. LVI Module Block Diagram
10.3.1 Polled LVI Operation
In applications that can operate at VDD levels below the VTRIPF level, software can
monitor VDD by polling the LVI5OR3 bit. In the mask option register, the LVIPWRD
bit must be at logic 0 to enable the LVI module, and the LVIRSTD bit must be at
logic 1 to disable LVI resets.
10.3.2 Forced Reset Operation
In applications that require VDD to remain above the VTRIPF level, enabling LVI
resets allows the LVI module to reset the MCU when VDD falls below the VTRIPF
level. In the mask option register, the LVIPWRD and LVIRSTD bits must be at
logic 0 to enable the LVI module and to enable LVI resets.
LOW VDD
DETECTOR
LVIPWRD
STOP INSTRUCTION
LVISTOP
LVI RESET
LVIOUT
VDD > LVITRIP = 0
VDD ≤ LVITRIP = 1
FROM MOR1
VDD
FROM MOR1
LVIRSTD
LVI5OR3
FROM MOR1
Addr.
Register Name
Bit 7
654321
Bit 0
$FE0C
LVI Status Register
(LVISR)
Read:
LVIOUT
0000000
Write:
Reset:
00000000
= Unimplemented
Figure 10-2. LVI I/O Register Summary
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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