參數(shù)資料
型號： MC68HC08GP8AMFB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP44
封裝： PLASTIC, QFP-44
文件頁數(shù)： 115/126頁
文件大?。?/td> 4243K
代理商： MC68HC08GP8AMFB
External Interrupt (IRQ)
IRQ Pin
MC68HC08GP8A
Data Sheet
MOTOROLA
External Interrupt (IRQ)
89
The vector fetch or software clear may occur before or after the interrupt pin returns
to logic 1. As long as the pin is low, the interrupt request remains pending. A reset
will clear the latch and the MODE control bit, thereby clearing the interrupt even if
the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt requests.
A latched interrupt request is not presented to the interrupt priority logic unless the
IMASK bit is clear.
NOTE:
The interrupt mask (I) in the condition code register (CCR) masks all interrupt
requests, including external interrupt requests.
7.4 IRQ Pin
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector
fetch, software clear, or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and
low-level-sensitive. With MODE set, both of the following actions must occur to
clear IRQ:
Vector fetch or software clear — A vector fetch generates an interrupt
acknowledge signal to clear the latch. Software may generate the interrupt
acknowledge signal by writing a logic 1 to the ACK bit in the interrupt status
and control register (INTSCR). The ACK bit is useful in applications that poll
the IRQ pin and require software to clear the IRQ latch. Writing to the ACK
bit prior to leaving an interrupt service routine can also prevent spurious
interrupts due to noise. Setting ACK does not affect subsequent transitions
on the IRQ pin. A falling edge that occurs after writing to the ACK bit another
interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the
program counter with the vector address at locations $FFFA and $FFFB.
Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic 0, IRQ
remains active.
The vector fetch or software clear and the return of the IRQ pin to logic 1 may occur
in any order. The interrupt request remains pending as long as the IRQ pin is at
logic 0. A reset will clear the latch and the MODE control bit, thereby clearing the
interrupt even if the pin stays low.
Addr.
Register Name
Bit 7
654321
Bit 0
$001D
IRQ Status and Control
Register (INTSCR)
Read:
0000
IRQF
0
IMASK
MODE
Write:
ACK
Reset:
00000000
= Unimplemented
Figure 7-3. IRQ I/O Register Summary
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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