參數(shù)資料
型號: MC68HC08GP8AMFB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP44
封裝: PLASTIC, QFP-44
文件頁數(shù): 21/126頁
文件大?。?/td> 4243K
代理商: MC68HC08GP8AMFB
MC68HC08GP8A
Data Sheet
MOTOROLA
Input/Output Ports (PORTS)
117
Data Sheet — MC68HC08GP8A
Section 12. Input/Output Ports (PORTS)
12.1 Introduction
Thirty-three (33) bidirectional input-output (I/O) pins form five parallel ports. All I/O
pins are programmable as inputs or outputs. All individual bits within port A, port C,
and port D are software configurable with pullup devices if configured as input port
bits. The pullup devices are automatically and dynamically disabled when a port bit
is switched to output mode.
NOTE:
Connect any unused I/O pins to an appropriate logic level, either VDD or VSS.
Although the I/O ports do not require termination for proper operation, termination
reduces excess current consumption and the possibility of electrostatic damage.
Addr.
Register Name
Bit 7
654321
Bit 0
$0000
Port A Data Register
(PTA)
Read:
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Write:
Reset:
Unaffected by reset
$0001
Port B Data Register
(PTB)
Read:
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
Write:
Reset:
Unaffected by reset
$0002
Port C Data Register
(PTC)
Read:
0
PTC6
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
Write:
Reset:
Unaffected by reset
$0003
Port D Data Register
(PTD)
Read:
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
Write:
Reset:
Unaffected by reset
$0004
Data Direction Register A
(DDRA)
Read:
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Write:
Reset:
00000000
$0005
Data Direction Register B
(DDRB)
Read:
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
Write:
Reset:
00000000
= Unimplemented
Figure 12-1. I/O Port Register Summary
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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