參數(shù)資料
型號： MC68HC08GP8AMFB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP44
封裝： PLASTIC, QFP-44
文件頁數(shù)： 117/126頁
文件大?。?/td> 4243K
代理商： MC68HC08GP8AMFB
External Interrupt (IRQ)
Data Sheet
MC68HC08GP8A
90
External Interrupt (IRQ)
MOTOROLA
Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch
remains set until one of the following actions occurs:
Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the latch that caused the vector fetch.
Software clear — Software can clear an interrupt latch by writing to the
appropriate acknowledge bit in the interrupt status and control register
(INTSCR). Writing a logic 1 to the ACK bit clears the IRQ latch.
Reset — A reset automatically clears the interrupt latch.
The external interrupt pin is falling-edge-triggered and is software-configurable to
be either falling-edge or falling-edge and low-level-triggered. The MODE bit in the
INTSCR controls the triggering sensitivity of the IRQ pin.
When an interrupt pin is edge-triggered only, the interrupt remains set until a vector
fetch, software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the interrupt
remains set until both of the following occur:
Vector fetch or software clear
Return of the interrupt pin to logic 1
If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE
clear, a vector fetch or software clear immediately clears the IRQ latch.
The IRQF bit in the INTSCR register can be used to check for pending interrupts.
The IRQF bit is not affected by the IMASK bit, which makes it useful in applications
where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
NOTE:
When using the level-sensitive interrupt trigger, avoid false interrupts by masking
interrupt requests in the interrupt routine.
7.5 IRQ Module During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables software to
clear the latch during the break state. See Section 19. Development Support.
To allow software to clear the IRQ latch during a break interrupt, write a logic 1 to
the BCFE bit. If a latch is cleared during the break state, it remains cleared when
the MCU exits the break state.
To protect CPU interrupt flags during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the ACK bit in the IRQ status
and control register during the break state has no effect on the IRQ interrupt flags.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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