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參數(shù)資料
| 型號： | MC68HC08GP8AMFB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 87/126頁 |
| 文件大?。?/td> | 4243K |
| 代理商： | MC68HC08GP8AMFB |
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Clock Generator Module (CGM)
CGM Registers
MC68HC08GP8A
Data Sheet
MOTOROLA
Clock Generator Module (CGM)
63
PMSH[7:4] — Unimplemented Bits
These bits have no function and always read as logic 0s.
4.5.4 PLL Multiplier Select Register Low
The PLL multiplier select register low (PMSL) contains the programming
information for the low byte of the modulo feedback divider.
MUL7–MUL0 — Multiplier Select Bits
These read/write bits control the low byte of the modulo feedback divider that
selects the VCO frequency multiplier, N. (See 4.3.3 PLL Circuits and 4.3.6
Programming the PLL.) MUL7–MUL0 cannot be written when the PLLON bit
in the PCTL is set. A value of $0000 in the multiplier select registers configures
the modulo feedback divider the same as a value of $0001. Reset initializes the
register to $40 for a default multiply value of 64.
NOTE:
The multiplier select bits have built-in protection such that they cannot be written
when the PLL is on (PLLON = 1).
4.5.5 PLL VCO Range Select Register
NOTE:
PMRS may be called PVRS on other HC08 derivatives.
The PLL VCO range select register (PMRS) contains the programming information
required for the hardware configuration of the VCO.
VRS7–VRS0 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear multiplier L
which, in conjunction with E (see 4.3.3 PLL Circuits, 4.3.6 Programming the
PLL, and 4.5.1 PLL Control Register), controls the hardware center-of-range
frequency, fVRS. VRS7–VRS0 cannot be written when the PLLON bit in the
PCTL is set. (See 4.3.7 Special Programming Exceptions.) A value of $00 in
the VCO range select register disables the PLL and clears the BCS bit in the
Address:
$0038
Bit 7
654321
Bit 0
Read:
MUL7
MUL6
MUL5
MUL4
MUL3
MUL2
MUL1
MUL0
Write:
Reset:
01000000
Figure 4-7. PLL Multiplier Select Register Low (PMSL)
Address:
$003A
Bit 7
654321
Bit 0
Read:
VRS7
VRS6
VRS5
VRS4
VRS3
VRS2
VRS1
VRS0
Write:
Reset:
01000000
Figure 4-8. PLL VCO Range Select Register (PMRS)
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