參數(shù)資料
型號(hào): MC68HC08GP8AMFB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP44
封裝: PLASTIC, QFP-44
文件頁數(shù): 82/126頁
文件大?。?/td> 4243K
代理商: MC68HC08GP8AMFB
Clock Generator Module (CGM)
CGM Registers
MC68HC08GP8A
Data Sheet
MOTOROLA
Clock Generator Module (CGM)
59
4.5.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag bits, the
on/off switch, the base clock selector bit, the prescaler bits, and the VCO
power-of-two range selector bits.
Addr.
Register Name
Bit 7
654321
Bit 0
$0036
PLL Control Register
(PCTL)
Read:
PLLIE
PLLF
PLLON
BCS
PRE1
PRE0
VPR1
VPR0
Write:
Reset:
00100000
$0037
PLL Bandwidth Control
Register (PBWC)
Read:
AUTO
LOCK
ACQ
0000
R
Write:
Reset:
00000000
$0038
PLL Multiplier Select High
Register (PMSH)
Read:
0000
MUL11
MUL10
MUL9
MUL8
Write:
Reset:
00000000
$0039
PLL Multiplier Select Low
Register (PMSL)
Read:
MUL7
MUL6
MUL5
MUL4
MUL3
MUL2
MUL1
MUL0
Write:
Reset:
01000000
$003A
PLL VCO Select Range
Register (PMRS)
Read:
VRS7
VRS6
VRS5
VRS4
VRS3
VRS2
VRS1
VRS0
Write:
Reset:
01000000
$003B
PLL Reference Divider
Select Register (PMDS)
Read:
0000
RDS3
RDS2
RDS1
RDS0
Write:
Reset:
00000001
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
= Unimplemented
R
= Reserved
Figure 4-3. CGM I/O Register Summary
Address:
$0036
Bit 7
654321
Bit 0
Read:
PLLIE
PLLF
PLLON
BCS
PRE1
PRE0
VPR1
VPR0
Write:
Reset:
00100000
= Unimplemented
Figure 4-4. PLL Control Register (PCTL)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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