參數(shù)資料
型號: MC68HC08GP8AMFB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP44
封裝: PLASTIC, QFP-44
文件頁數(shù): 68/126頁
文件大?。?/td> 4243K
代理商: MC68HC08GP8AMFB
Analog-to-Digital Converter (ADC)
Data Sheet
MC68HC08GP8A
46
Analog-to-Digital Converter (ADC)
MOTOROLA
3.7.3 ADC Clock Register
The ADC clock register (ADCLK) selects the clock frequency for the ADC.
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC
to generate the internal ADC clock. Table 3-2 shows the available clock
configurations. The ADC clock should be set to approximately 1 MHz.
ADICLK — ADC Input Clock Select Bit
ADICLK selects either the bus clock or CGMXCLK as the input clock source to
generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock
source.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK
can be used as the clock source for the ADC. If CGMXCLK is less than 1 MHz,
use the PLL-generated bus clock as the clock source. As long as the internal
ADC clock is at approximately 1 MHz, correct operation can be guaranteed.
1 = Internal bus clock
0 = External clock (CGMXCLK)
Address:
$003E
Bit 7
654321
Bit 0
Read:
ADIV2
ADIV1
ADIV0
ADICLK
0000
Write:
Reset:
00000000
= Unimplemented
Figure 3-5. ADC Clock Register (ADCLK)
Table 3-2. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
ADC Clock Rate
0
ADC input clock
÷ 1
0
1
ADC input clock
÷ 2
0
1
0
ADC input clock
÷ 4
0
1
ADC input clock
÷ 8
1
X
ADC input clock
÷ 16
X = don’t care
ADC input clock frequency
ADIV2 ADIV0
-----------------------------------------------------------------------
1MHz
=
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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