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參數(shù)資料
| 型號(hào)： | MC68HC08GP8AMFB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 67/126頁 |
| 文件大?。?/td> | 4243K |
| 代理商： | MC68HC08GP8AMFB |
Analog-to-Digital Converter (ADC)
I/O Registers
MC68HC08GP8A
Data Sheet
MOTOROLA
Analog-to-Digital Converter (ADC)
45
The ADC subsystem is turned off when the channel select bits are all set to 1.
This feature allows for reduced power consumption for the MCU when the ADC
is not being used.
NOTE:
Recovery from the disabled state requires one conversion cycle to stabilize.
The voltage levels supplied from internal reference nodes, as specified in
Table 3-1, are used to verify the operation of the ADC converter both in production
test and for user applications.
3.7.2 ADC Data Register
One 8-bit result register, ADC data register (ADR), is provided. This register is
updated each time an ADC conversion completes.
Table 3-1. Mux Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
Input Select
0
000
0
PTB0/AD0
0
000
1
PTB1/AD1
0
001
0
PTB2/AD2
0
001
1
PTB3/AD3
0
010
0
PTB4/AD4
0
010
1
PTB5/AD5
0
011
0
PTB6/AD6
0
011
1
PTB7/AD7
0
100
0
Reserved
↓↓↓
↓↓
1
110
0
1
110
1
VREFH
1
111
0
VREFL
1
111
1
ADC power off
NOTE:
If any unused channels are selected, the resulting ADC conversion will be unknown
or reserved.
Address:
$003D
Bit 7
654321
Bit 0
Read:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:
00000000
= Unimplemented
Figure 3-4. ADC Data Register (ADR)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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