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| 型號(hào)： | MC68HC08GP8AMFB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 74/126頁(yè) |
| 文件大?。?/td> | 4243K |
| 代理商： | MC68HC08GP8AMFB |
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Clock Generator Module (CGM)
Functional Description
MC68HC08GP8A
Data Sheet
MOTOROLA
Clock Generator Module (CGM)
51
4.3.5 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually
or automatically. Automatic mode is recommended for most users.
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically
switches between acquisition and tracking modes. Automatic bandwidth control
mode also is used to determine when the VCO clock, CGMVCLK, is safe to use as
the source for the base clock, CGMOUT. (See 4.5.2 PLL Bandwidth Control
Register.) If PLL interrupts are enabled, the software can wait for a PLL interrupt
request and then check the LOCK bit. If interrupts are disabled, software can poll
the LOCK bit continuously (during PLL startup, usually) or at periodic intervals. In
either case, when the LOCK bit is set, the VCO clock is safe to use as the source
for the base clock. (See 4.3.8 Base Clock Selector Circuit.) If the VCO is selected
as the source for the base clock and the LOCK bit is clear, the PLL has suffered a
severe noise hit and the software must take appropriate action, depending on the
application. (See 4.6 Interrupts for information and precautions on using
interrupts.)
The following conditions apply when the PLL is in automatic bandwidth control
mode:
The ACQ bit (see 4.5.2 PLL Bandwidth Control Register) is a read-only
indicator of the mode of the filter. (See 4.3.4 Acquisition and Tracking
The ACQ bit is set when the VCO frequency is within a certain tolerance and
is cleared when the VCO frequency is out of a certain tolerance. (See 4.8
Acquisition/Lock Time Specifications for more information.)
The LOCK bit is a read-only indicator of the locked state of the PLL.
The LOCK bit is set when the VCO frequency is within a certain tolerance
and is cleared when the VCO frequency is out of a certain tolerance. (See
4.8 Acquisition/Lock Time Specifications for more information.)
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock
condition changes, toggling the LOCK bit. (See 4.5.1 PLL Control
Register.)
The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by
systems that do not require an indicator of the lock condition for proper operation.
Such systems typically operate well below fBUSMAX.
The following conditions apply when in manual mode:
ACQ is a writable control bit that controls the mode of the filter. Before
turning on the PLL in manual mode, the ACQ bit must be clear.
Before entering tracking mode (ACQ = 1), software must wait a given time,
PLL by setting PLLON in the PLL control register (PCTL).
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