參數(shù)資料
型號: MC68HC05T16B
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝: PLASTIC, SDIP-56
文件頁數(shù): 92/128頁
文件大小: 734K
代理商: MC68HC05T16B
MOTOROLA
7-2
MC68HC05T16
PULSE ACCUMULATOR
7
PAEN - PAC Enable Bit
1 (set)
Pulse Accumulator enabled.
0 (clear) –
Pulse Accumulator disabled. PAC counter register is also cleared.
PAMOD - Pulse Accumulator Mode Bit
1 (set)
Gated time accumulation mode.
0 (clear) –
External event counting mode.
PAIE - PAC Interrupt Enable Bit
1 (set)
PAC overow Interrupt enabled.
0 (clear) –
PAC overow Interrupt disabled.
This PAIE bit enables interrupt caused by the PAOF bit.
7.1.2
PAC Counter Register
When PAC is disabled (PAEN=0), the counter will be cleared to zero. This ensures the Counter
starts from zero every time it is disabled and enabled.
The Pulse Accumulator Counter is read only and resets to zero a write operation.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0F
PAD7
PAD6
PAD5
PAD4
PAD3
PAD2
PAD1
PAD0
0000 0000
TPG
64
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