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參數(shù)資料
| 型號： | MC68HC05T16B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | PLASTIC, SDIP-56 |
| 文件頁數(shù)： | 61/128頁 |
| 文件大?。?/td> | 734K |
| 代理商： | MC68HC05T16B |
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MOTOROLA
4-8
MC68HC05T16
RESETS AND INTERRUPTS
4
4.2.4
Programmable Timer Interrupt
Four timer interrupt ags are found in the top nibble of the Timer Status register (TSR) at location
$11. All four interrupts will vector to the same address at location $FFF6-$FFF7.
Each ag bit is dened as follows:
TOF - Timer Overow Flag
TOF is set during the counter transition of $FFFF to $0000. It is cleared by
reading the TSR (with TOF set) followed by reading the counter least signicant
byte ($19).
OC0F, OC1F - Output Compare Flag 1 and Output Compare 2
The appropriate OCF is set when the corresponding Output Compare register
matches the Counter register. It is cleared by reading the TSR (with OCF set)
and then accessing the corresponding Output Compare register least signicant
byte ($15 or $17).
ICF - Input Capture Flag
ICF is set when a proper edge has been sensed by the input capture edge
detector. It is cleared by an CPU read of the TSR (with ICF set) followed by
accessing the Input Capture register least signicant byte ($13).
All four timer interrupt ags have corresponding enable bits (ICIE, OC0IE, OC1IE, and TOIE)
found in the Timer Control register (TCR) at location $10. Reset clears all enable bits preventing
an interrupt from occurring. The actual processor interrupt is generated only if the interrupt mask
bit of the condition code register is also cleared. When the interrupt is recognized, the current state
of the machine is pushed onto the stack and the interrupt mask bit in the condition code register
is set. This masks further interrupts until the present one is serviced. The service routine address
is specied by the contents of $FFF6 and $FFF7.
Refer to section 5.1 for detailed description of Programmable Timer.
4.2.5
M-Bus Interrupts
M-Bus interrupt is enabled when the M-Bus Interrupt Enable bit, MIEN of M-Bus Control register
is set, provided the interrupt mask bit of the condition code register is cleared. There are three
causes of M-Bus interrupt:
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer Status Register
$11
ICF
OC0F
OC1F
TOF
TCAPS
0
0000 u000
TPG
36
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