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參數(shù)資料
| 型號： | MC68HC05T16B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | PLASTIC, SDIP-56 |
| 文件頁數(shù)： | 11/128頁 |
| 文件大?。?/td> | 734K |
| 代理商： | MC68HC05T16B |
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MOTOROLA
12-2
MC68HC05T16
LOW POWER MODES
12
12.1.2
M-Bus during Stop Mode
When Stop mode is entered, the internal clock driving the M-Bus module will be held at a static
state, thus disabling the operation of the M-Bus module. The M-Bus module hence cannot wake
up the CPU.
12.1.3
Pulse Accumulator during Stop Mode
When Stop mode is entered, the internal clock driving the Pulse Accumulator module will be held
at a static state, thus disabling the operation of the Pulse Accumulator module. The Pulse
Accumulator module hence cannot wake up the CPU.
12.1.4
PWM during Stop Mode
When Stop mode is entered, the internal clock driving the PWM module will be held at a static
state, thus disabling the operation of the PWM module. The PWM module hence cannot wake up
the CPU.
12.1.5
OSD during Stop Mode
When Stop mode is entered, the internal clock driving most of the OSD logic will be held at a static
state, disabling the operation of the OSD module. If the PLL is not stopped by clearing PLLEN bit,
the OSD pixel clock will still run, causing power consumption in Stop mode. The OSD module
cannot wake up the CPU when in Stop mode.
12.1.6
ADC during Stop Mode
The ADC module operates with the presence of the internal clock, therefore, in Stop mode, ADC
operation is halted.
12.1.7
COP during Stop Mode
The COP watchdog system stops counting in Stop mode. It continues counting again after 4069
bus cycles when the exit is caused by a external interrupt on IRQ. If exit from Stop mode was
caused by a reset, the MCU will be initialized and the COP watchdog system will be disabled.
TPG
106
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