參數(shù)資料
型號: MC68HC05T16B
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝: PLASTIC, SDIP-56
文件頁數(shù): 112/128頁
文件大小: 734K
代理商: MC68HC05T16B
MOTOROLA
9-14
MC68HC05T16
ON-SCREEN DISPLAY
9
9.5.1
Frame Control 1 and Row Count Register
Bits 7 to 4 are control bits and, bits 3 to 0 are status bits.
PLLEN - PLL enable bit
1 (set)
PLL enabled for OSD clock source.
0 (clear) –
PLL disabled.
DSCAN - Double/Single scan mode select
1 (set)
Double scan mode.
0 (clear) –
Single scan mode.
DSCAN (double scan) bit is for the control of OSD logic so that the OSD can accommodate
non-interlaced scan TV system by adjusting dot matrix scan output. Users have to determine if the
target TV broadcast system is a double scan system. If DSCAN is set, all horizontal lines in the
character dot matrix will be displayed twice in the same frame. The other feature associated with
horizontal lines that will also be doubled is the RiVP6-RiVP0 eld of Row Vertical Position
Registers.
FADE - Display fade enable
1 (set)
Display fade function enabled.
0 (clear) –
Display fade function disabled.
The FADE bit controls the sequence of frame display appearance and disappearance. When
FADE bit is set, frame display will gradually appear (fade in) if ON/OFF is set, and gradually
disappear (fade out) if ON/OFF is clear. If FADE bit is clear, OSD display will be turned on or off
instantly.
Table 9-2 Number of Visible Characters Per Row
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$1D
PLLEN
DSCAN
FADE
ON/OFF
CDRC3
CDRC2
CDRC1
CDRC0
0000 0000
1H x 1V
2H x 2V
3H x 3V
4H x 4V
24
12
8
6
8
11
16
32
16x16
12x16
dot matrix
char size
TPG
82
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