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參數(shù)資料
| 型號： | MC68HC05T16B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | PLASTIC, SDIP-56 |
| 文件頁數(shù)： | 46/128頁 |
| 文件大小： | 734K |
| 代理商： | MC68HC05T16B |
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MOTOROLA
2-4
MC68HC05T16
PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS
2
2.2
INPUT/OUTPUT PORTS
2.2.1
Input/Output Programming
Port A, B, C, E, and F may be programmed as an input or an output under software control. The
direction of the pins is determined by the state of corresponding bit in the port data direction
register (DDR). Each 8-bit port has an associated 8-bit data direction register. Any port A, B, C,
E, or F pin is congured as an output if its corresponding DDR bit is set to a logic one. A pin is
congured as an input if its corresponding DDR bit is cleared to a logic zero. At power-on or reset,
all DDRs are cleared, which congure all port A, B, C, E and F pins as inputs. The data direction
registers are capable of being written to or read by the processor. Refer to Figure 2-2 and
Table 2-1. During the programmed output state, a read of the data register actually reads the value
of the output data latch and not the I/O pin.
2.2.2
Port E and F Conguration Registers
Port E and F are shared with PWM, PAC, OSD, MBUS, and ADC. The conguration registers, at
$0C and $0D, are used to congure these I/O pins. The default state after a reset or POR is zero.
Setting the corresponding bits will enable the corresponding functions. For example, setting the
SDA and SCL bits will congure PF5 and PF6 as MBUS interface pins, regardless of the settings
in the port F Data Direction register.
Table 2-1 I/O Pin Functions
R/W
DDR
I/O Pin Function
0
The I/O pin is in input mode. Data is written into the output data latch.
0
1
Data is written into the output data latch and output to the I/O pin.
1
0
The state of the I/O pin is read.
1
The I/O pin is in an output mode. The output data latch is read.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Port E Conguration Register
$0C
PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 0000 0000
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Port F Conguration Register
$0D
PAC
SCL
SDA
ADC1 HTONE
I
PWM9 PWM8 0000 0000
TPG
22
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