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參數(shù)資料
| 型號： | MC68HC05T16B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | PLASTIC, SDIP-56 |
| 文件頁數(shù)： | 62/128頁 |
| 文件大?。?/td> | 734K |
| 代理商： | MC68HC05T16B |
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MC68HC05T16
MOTOROLA
4-9
RESETS AND INTERRUPTS
4
1) An arbitration lost which is signied by the Arbitration Lost ag, ALOST of
M-Bus Status Register.
2) Addressed as slave which is indicated by the master addressed as slave
ag, SELTED of M-Bus Status Register.
3) Completed transmission or reception of one byte of data. It depends on the
original mode of the M-Bus interface which is determined by the
Transmit/Receive ag, XMT of M-Bus Control Register.
MCF - Data Transfer Complete Flag
1 (set)
–
A byte transfer has been completed.
0 (clear) –
A byte is being transfer.
SELTED - Addressed as Slave
1 (set)
–
Currently addressed as a slave.
0 (clear) –
Currently not addressed.
When its own specic address (M-Bus Address register) matches the calling address, this bit is
set. An interrupt is generated if the MIEN bit is set. Then CPU needs to check the SRW bit and set
its XMT bit accordingly. Writing to the M-Bus Control register clears this bit.
ALOST - Arbitration Lost
This arbitration lost bit is set by hardware when the M-bus master loses arbitration during a master
transmission mode. This bit must be cleared by software.
On entering the interrupt service routine, the M-Bus interrupt ag, MIF of M-Bus Status Register
must be cleared by software.
The interrupt service routine address is specied by the contents of memory location $FFF4 and
$FFF5. Reset disables the whole M-Bus block by clearing the M-Bus Control Register.
Refer to Section 6 for detailed description of M-Bus.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
M-Bus Status Register
$3A
MCF SELTED BBSY ALOST
SRW
MIF
RXACKB
1000 0001
TPG
37
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