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參數(shù)資料
| 型號： | MC68HC05F4FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.789 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 90/130頁 |
| 文件大?。?/td> | 2089K |
| 代理商： | MC68HC05F4FB |
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MOTOROLA
6-12
MC68HC05F4
16-BIT PROGRAMMABLE TIMER
6
The purpose of this procedure is to prevent the OC1F bit from being set between the time it is read
and the write to the corresponding output compare register.
All bits of the output compare register are readable and writable and are not altered by the timer
hardware or reset. If the compare function is not needed, the two bytes of the output compare
register can be used as storage locations.
6.4.2
Output compare register 2 (OCR2)
The 16-bit output compare register 2 is made up of two 8-bit registers at locations $0026 (MSB)
and $0027 (LSB). The contents of the output compare register 2 are compared with the contents
of the free-running counter continually and, if a match is found, the corresponding output compare
ag (OC2F) in the timer status register is set. If the timer compare 2 output enable bit (CO2E) is
set, the output level (OLVL2) is transferred to pin TCMP2. The output compare register 2 values
and the output level bit should be changed after each successful comparison to establish a new
elapsed timeout. An interrupt can also accompany a successful output compare provided the
corresponding interrupt enable bit (OC2IE) is set. (The free-running counter is updated every four
internal bus clock cycles.)
After a processor write cycle to the output compare register 2 containing the MSB ($0026), the
output compare function is inhibited until the LSB ($0027) is also written. The user must write both
bytes (locations) if the MSB is written rst. A write made only to the LSB ($0027) will not inhibit the
compare 2 function. The processor can write to either byte of the output compare register 2 without
affecting the other byte. If the timer compare output enable bit (CO2E) is set, the output level
(OLVL2) bit is clocked to the output level register and hence to the TCMP2 pin whether the output
compare 2 ag (OC2F) is set or clear. The minimum time required to update the output compare
register 2 is a function of the program rather than the internal hardware. Because the output
compare 2 ag and the output compare register 2 are not dened at power on, and not affected
by reset, care must be taken when initializing output compare functions with software. The
following procedure is recommended:
–
Write to output compare 2 high to inhibit further compares;
–
Read the timer status register to clear OC2F (if set);
–
Write to output compare 2 low to enable the output compare 2 function.
The purpose of this procedure is to prevent the OC2F bit from being set between the time it is read
and the write to the corresponding output compare register.
All bits of the output compare register are readable and writable and are not altered by the timer
hardware or reset. If the compare function is not needed, the two bytes of the output compare
register can be used as storage locations.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Output compare 2 high (OCR2H)
$0026
Undened
Output compare 2 low (OCR2H)
$0027
Undened
TPG
58
05F4Book Page 12 Tuesday, August 5, 1997 1:10 pm
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