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參數(shù)資料
| 型號： | MC68HC05F4FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.789 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 84/130頁 |
| 文件大?。?/td> | 2089K |
| 代理商： | MC68HC05F4FB |
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MC68HC05F4
MOTOROLA
6-7
16-BIT PROGRAMMABLE TIMER
6
6.2.2
Timer status register (TSR)
The timer status register ($002E) contains the status bits corresponding to the timer interrupt
conditions – IC1F, IC2F, OC1F, TOF, TCAP1, TCAP2 and OC2F.
Accessing the timer status register satises the rst condition required to clear the status bits. The
remaining step is to access the register corresponding to the status bit.
IC1F — Input capture 1 ag
This bit is set when the selected polarity of edge is detected by the input capture edge detector 1
at TCAP1; an input capture interrupt will be generated, if IC1IE is set. IC1F is cleared by reading
the TSR and then the input capture 1 low register ($0021).
1 (set)
–
A valid input capture has occurred.
0 (clear) –
No input capture has occurred.
IC2F — Input capture 2 ag
This bit is set when the selected polarity of edge is detected by the input capture edge detector 2
at TCAP2; an input capture interrupt will be generated if IC2IE is set. IC2F is cleared by reading
the TSR and then the input capture 2 low register ($0025).
1 (set)
–
A valid input capture has occurred.
0 (clear) –
No input capture has occurred.
OC1F — Output compare 1 ag
This bit is set when the output compare register 1 contents match those of the free-running
counter; an output compare interrupt will be generated if OC1IE is set. OC1F is cleared by reading
the TSR and then the output compare 1 low register ($0023).
1 (set)
–
A valid output compare has occurred.
0 (clear) –
No output compare has occurred.
TOF — Timer overow status ag
This bit is set when the free-running counter overows from $FFFF to $0000; a timer overow interrupt
will occur if TOIE is set. TOF is cleared by reading the TSR and the counter low register ($0029).
1 (set)
–
Timer overow has occurred.
0 (clear) –
No timer overow has occurred.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer status (TSR)
$002E
IC1F
IC2F
OC1F
TOF
TCAP1 TCAP2 OC2F
0
uuuu uuu0
TPG
53
05F4Book Page 7 Tuesday, August 5, 1997 1:10 pm
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