參數(shù)資料
型號(hào): MC68HC05F4FB
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 1.789 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數(shù): 83/130頁
文件大?。?/td> 2089K
代理商: MC68HC05F4FB
MOTOROLA
6-6
MC68HC05F4
16-BIT PROGRAMMABLE TIMER
6
IEDG2 — Input edge 2
When IEDG2 is set, a positive-going edge on the TCAP2 pin will trigger a transfer of the
free-running counter value to the input capture register 2. When clear, a negative-going edge
triggers the transfer.
1 (set)
TCAP2 is positive-going edge sensitive.
0 (clear) –
TCAP2 is negative-going edge sensitive.
OLVL1 — Output level 1
When OLV1 is set a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP1 pin. When clear, it will be a low level
which will appear on the TCMP1 pin.
1 (set)
A high output level will appear on the TCMP1 pin.
0 (clear) –
A low output level will appear on the TCMP1 pin.
OC2IE — Output compare 2 interrupt enable
If this bit is set, a timer interrupt is enabled whenever the OC2F status ag (in the timer status
register) is set.
1 (set)
Interrupt enabled.
0 (clear) –
Interrupt disabled.
CO2E — Timer compare 2 output enable
If this bit is set, the output from timer output compare 2 is enabled.
1 (set)
Output compare 2 enabled.
0 (clear) –
Output compare 2 disabled.
OLVL2 — Output level 2
When OLV2 is set a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP2 pin. When clear, it will be a low level
which will appear on the TCMP2 pin.
1 (set)
A high output level will appear on the TCMP2 pin.
0 (clear) –
A low output level will appear on the TCMP2 pin.
TPG
52
05F4Book Page 6 Tuesday, August 5, 1997 1:10 pm
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