參數(shù)資料
型號: MC68HC05F4FB
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 1.789 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數(shù): 74/130頁
文件大?。?/td> 2089K
代理商: MC68HC05F4FB
MOTOROLA
5-4
MC68HC05F4
CORE TIMER
5
RTOF — Reset timer overow ag
Writing a ‘1’ to this bit clears the timer overow ag, CTOF. See CTOF description.
RRTIF — Reset real time overow ag
Wrting a ‘1’ to this bit clears the real time interrupt ag, RTIF. See RTIF description.
RT1, RT0 — Real time interrupt rate select
These two bits select one of four taps from the real time interrupt circuitry. Reset sets both RT0
and RT1 to one, selecting the lowest periodic rate and therefore the maximum time in which to
alter them if necessary. The COP reset times are also determined by these two bits. Care should
be taken when altering RT0 and RT1 if a timeout is imminent, or the timeout period is uncertain.
If the selected tap is modied during a cycle in which the counter is switching, an RTIF could be
missed or an additional one could be generated. To avoid problems, the COP should be cleared
before changing the RTI taps. See Table 5-1 for some example RTI periods.
5.2.2
Core timer counter register (CTCR)
The core timer counter register is a read-only register, which contains the current value of the 8-bit
ripple counter at the beginning of the timer chain. Reset clears this register.
Table 5-1 Example RTI periods
RTI Rates at fOP Frequency Specied
RT1 RT0
Division
ratio
16.384 kHz
447 kHz
895 kHz
1.789 MHz
00
214
1 s
36.7 ms
18.35 ms
9.17 ms
01
215
2 s
73.4 ms
36.7 ms
18.35 ms
10
216
4 s
146.8 ms
73.4 ms
36.7 ms
11
217
8 s
293.6 ms
146.8 ms
73.4 ms
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Core timer counter (CTCR)
$0009
0000 0000
TPG
44
05F4Book Page 4 Tuesday, August 5, 1997 1:10 pm
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