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| 型號(hào)： | MC68HC05F4FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.789 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁(yè)數(shù)： | 80/130頁(yè) |
| 文件大小： | 2089K |
| 代理商： | MC68HC05F4FB |
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MC68HC05F4
MOTOROLA
6-3
16-BIT PROGRAMMABLE TIMER
6
6.1.1
Counter register and alternate counter register
The double-byte, free-running counter can be read from either of two locations, $0028 – $0029
(counter register) or $002A – $002B (counter alternate register). A read from only the less
signicant byte (LSB) of the free-running counter ($0029 or $002B) receives the count value at the
time of the read. If a read of the free-running counter or alternate counter register rst addresses
the more signicant byte (MSB) ($0028 or $002A), the LSB is transferred to a buffer. This buffer
value remains xed after the rst MSB read, even if the user reads the MSB several times. This
buffer is accessed when reading the free-running counter or alternate counter register LSB and
thus completes a read sequence of the total counter value. In reading either the free-running
counter or alternate counter register, if the MSB is read, the LSB must also be read to complete
the sequence. If the timer overow ag (TOF) is set when the counter register LSB is read then a
read of the timer status register (TSR) will clear the ag.
The counter alternate register differs from the counter register only in that a read of the LSB does
not clear TOF. Therefore, where it is critical to avoid the possibility of missing timer overow
interrupts due to clearing of TOF, the alternate counter register should be used.
The free-running counter is set to $FFFC during power-on and external reset and is always a
read-only register. During a power-on reset, the counter begins running after the oscillator start-up
delay. Because the free-running counter is 16 bits preceded by a xed divide-by-4 prescaler, the
value in the free-running counter repeats every 262,144 internal bus clock cycles. TOF is set when
the counter overows (from $FFFF to $0000); this will cause an interrupt if TOIE is set.
The divide-by-4 prescaler is also reset and the counter resumes normal counting operation. All of
the ags and enable bits remain unaltered by this operation. If access has previously been made
to the high byte of the free-running counter ($0028 or $002A), then the reset counter operation
terminates the access sequence.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer counter high (CNTH)
$0028
1111 1111
Timer counter low (CNTL)
$0029
1111 1100
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Alternate counter high (ACNTH)
$002A
1111 1111
Alternate counter low (ACNTL)
$002B
1111 1100
TPG
49
05F4Book Page 3 Tuesday, August 5, 1997 1:10 pm
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