參數(shù)資料
型號(hào)： MC68CK338CPV14B1
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 14.4 MHz, MICROCONTROLLER, PQFP144
封裝： PLASTIC, TQFP-144
文件頁數(shù)： 72/133頁
文件大?。?/td> 944K
代理商： MC68CK338CPV14B1
MC68CK338
MOTOROLA
MC68CK338TS/D
43
3.8.3 Functions of Pins for Other Modules During Reset
Generally, pins associated with modules other than the SIML default to port functions, and input/output
ports are set to input state. This is accomplished by disabling pin functions in the appropriate control
registers, and by clearing the appropriate port data direction registers. Refer to individual module sec-
tions in this manual for more information.
3.8.4 Reset Timing
The RESET input must be asserted for a specified minimum period in order for reset to occur. External
RESET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus
monitor time-out period) in order to protect write cycles from being aborted by reset. While RESET is
asserted, SIML pins are either in a disabled high-impedance state or are driven to their inactive states.
When an external device asserts RESET for the proper period, reset control logic clocks the signal into
an internal latch. The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after
it detects that the RESET signal is no longer being externally driven, to guarantee this length of reset
to the entire system.
Table 32 SIML Pin Reset States
Pin(s)
Pin State
While RESET
Asserted
Pin State After RESET Released
Default Function
Alternate Function
Pin Function
Pin State
Pin Function
Pin State
CS10/ADDR23/ECLK
VDD
CS10
VDD
ADDR23
Unknown
CS[9:6]/ADDR[22:19]/PC[6:3]
VDD
CS[9:6]
VDD
ADDR[22:19]
Unknown
ADDR[18:0]
High-Z
ADDR[18:0]
Unknown
ADDR[18:0]
Unknown
AS/PE5
High-Z
AS
Output
PE5
Input
AVEC/PE2
High-Z
AVEC
Input
PE2
Input
BERR
High-Z
BERR
Input
BERR
Input
CS1/BG
VDD
CS1
VDD
BG
VDD
CS2/BGACK
VDD
CS2
VDD
BGACK
Input
CS0/BR
VDD
CS0
VDD
BR
Input
CLKOUT
Output
CLKOUT
Output
CLKOUT
Output
CSBOOT
VDD
CSBOOT
VSS
CSBOOT
VSS
DATA[15:0]
Mode select
DATA[15:0]
Input
DATA[15:0]
Input
DS/PE4
High-Z
DS
Output
PE4
Input
DSACK0/PE0
High-Z
DSACK0
Input
PE0
Input
DSACK1/PE1
High-Z
DSACK1
Input
PE1
Input
CS[5:3]/FC[2:0]/PC[2:0]
VDD
CS[5:3]
VDD
FC[2:0]
Unknown
HALT
High-Z
HALT
Input
HALT
Input
IRQ[7:1]/PF[7:1]
High-Z
IRQ[7:1]
Input
PF[7:1]
Input
MODCLK/PF0
Mode Select
MODCLK
Input
PF0
Input
R/W
High-Z
R/W
Output
R/W
Output
RESET
Asserted
RESET
Input
RESET
Input
RMC/PE3
High-Z
RMC
Output
PE3
Input
SIZ[1:0]/PE[7:6]
High-Z
SIZ[1:0]
Unknown
PE[7:6]
Input
TSC
Mode select
TSC
Input
TSC
Input
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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