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| 型號(hào)： | MC68CK338CPV14B1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 14.4 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 22/133頁 |
| 文件大小： | 944K |
| 代理商： | MC68CK338CPV14B1 |
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MOTOROLA
MC68CK338
118
MC68CK338TS/D
NOTES:
1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.
2. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum
allowable tXcyc period is reduced when the duty cycle of the external clock varies. The relationship between ex-
ternal clock input duty cycle and minimum tXcyc is expressed:
Minimum tXcyc period = minimum tXCHL / (50% – external clock input duty cycle tolerance).
3. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the relative
loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS to fall out-
side the limits shown in specification 9.
4. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the negation of a
heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated specification
between multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles.
5. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast
cycle reads. The user is free to use either hold time.
6. Maximum value is equal to (tcyc / 2) + 25 ns.
7. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK[1:0] low to data setup
time (specification 31) and DSACK[1:0] low to BERR low setup time (specification 48) can be ignored. The data
must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. BERR must
satisfy only the late BERR low to clock low setup time (specification 27A) for the following clock cycle.
8. To ensure coherency during every operand transfer, BG is not asserted in response to BR until after all cycles
of the current operand transfer are complete.
9. In the absence of DSACK[1:0], BERR is an asynchronous input using the asynchronous setup time (specification
47A).
10. After external RESET negation is detected, a short transition period (approximately 2 tcyc) elapses, then the SIML
drives RESET low for 512 tcyc.
11. External assertion of the RESET input can overlap internally-generated resets. To ensure that an external reset
is recognized in all cases, RESET must be asserted for at least 590 CLKOUT cycles.
12. External logic must pull RESET high during this period in order for normal MCU operation to begin.
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For More Information On This Product,
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