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| 型號(hào)： | MC68CK338CPV14B1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 14.4 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁(yè)數(shù)： | 55/133頁(yè) |
| 文件大小： | 944K |
| 代理商： | MC68CK338CPV14B1 |
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MOTOROLA
MC68CK338
28
MC68CK338TS/D
3.5.6 Data Strobe
Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an external device
to place data on the bus. DS is asserted at the same time as AS during a read cycle. For a write cycle,
DS signals an external device that data on the bus is valid. The MCU asserts DS one full clock cycle
after the assertion of AS during a write cycle.
3.5.7 Bus Cycle Termination Signals
During bus cycles, external devices assert the data size acknowledge signals DSACK1 and DSACK0.
During a read cycle, the signals tell the MCU to terminate the bus cycle and to latch data. During a write
cycle, the signals indicate that an external device has successfully stored data and that the cycle can
end. These signals also indicate to the MCU the size of the port for the bus cycle just completed. Alter-
nately, chip-selects can be used to generate DSACK1 and DSACK0 internally. Refer to 3.5.8 Dynamic
Bus Sizing for more information.
The bus error (BERR) signal is also a bus cycle termination indicator and can be used in the absence
of DSACK1 and DSACK0 to indicate a bus error condition. It can also be asserted in conjunction with
these signals, provided it meets the appropriate timing requirements. The internal bus monitor can be
used to generate the BERR signal for internal-to-external transfers. When BERR and HALT are assert-
ed simultaneously, the CPU takes a bus error exception.
The autovector signal (AVEC) can terminate IRQ pin interrupt acknowledge cycles. AVEC indicates that
the MCU will internally generate a vector number to locate an interrupt handler routine. If it is continu-
ously asserted, autovectors will be generated for all external interrupt requests. AVEC is ignored during
all other bus cycles.
3.5.8 Dynamic Bus Sizing
The MCU dynamically interprets the port size of the addressed device during each bus cycle, allowing
operand transfers to or from 8- and 16-bit ports. During an operand transfer cycle, the slave device sig-
nals its port size and indicates completion of the bus cycle to the MCU through the use of the DSACK1
and DSACK0 inputs, as shown in Table 15.
For example, if the MCU is executing an instruction that reads a long-word operand from a 16-bit port,
the MCU latches the 16 bits of valid data and then runs another bus cycle to obtain the other 16 bits.
The operation for an 8-bit port is similar, but requires four read cycles. The addressed device uses the
DSACK0 and DSACK1 signals to indicate the port width. For instance, a 16-bit device always returns
DSACK0 = 1 and DSACK1 = 0 for a 16-bit port, regardless of whether the bus cycle is a byte or word
operation.
Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular
port size be fixed. A 16-bit port must reside on data bus bits [15:0] and an 8-bit port must reside on data
bus bits [15:8]. This minimizes the number of bus cycles needed to transfer data and ensures that the
MCU transfers valid data.
Table 15 Effect of DSACK Signals
DSACK1
DSACK0
Result
1
Insert Wait States in Current Bus Cycle
1
0
Complete Cycle — Data Bus Port Size is 8 Bits
0
1
Complete Cycle — Data Bus Port Size is 16 Bits
0
Reserved
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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