參數(shù)資料
型號(hào)： MC68CK338CPV14B1
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 14.4 MHz, MICROCONTROLLER, PQFP144
封裝： PLASTIC, TQFP-144
文件頁(yè)數(shù)： 44/133頁(yè)
文件大小： 944K
代理商： MC68CK338CPV14B1
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MOTOROLA
MC68CK338
18
MC68CK338TS/D
Figure 7 System Clock Filter Network
When the clock synthesizer is used, SYNCR determines the operating frequency of the MCU. The fol-
lowing equation relates the MCU operating frequency to the clock synthesizer reference frequency (fref)
and the W, X, and Y fields in the SYNCR:
The W bit controls a prescaler tap in the feedback divider. Setting W increases VCO speed by a factor
of four. The Y field determines the count modulus for a modulo 64 downcounter, causing it to divide by
a value of Y+1. When W or Y changes, VCO frequency (fVCO) changes, and the VCO must relock.
The X bit controls a divide-by-two circuit that is not in the synthesizer feedback loop. When X=0 (reset
state), the divider is enabled, and the system clock is one-fourth the VCO frequency. Setting X=1
disables the divider, doubling the clock speed without changing the VCO frequency. There is no relock
delay when clock speed is changed by the X bit.
Internal VCO frequency is determined by the following equations:
or
For the MCU to operate correctly, system clock and VCO frequencies selected by the W, X, and Y bits
must be within the limits specified for the MCU. Do not use a combination of bit values that selects either
an operating frequency or a VCO frequency greater than the maximum specified values.
3.3.3 Clock Synthesizer Control
The clock synthesizer control circuits determine system clock frequency and clock operation under spe-
cial circumstances, such as following loss of synthesizer reference or during low-power operation. Clock
source is determined by the logic state of the MODCLK pin during reset.
NOTES:
1. Ensure that initialization software does not change the value of this bit (it should always be zero).
SYNCR — Clock Synthesizer Control Register
$YFFA04
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
X
Y
EDIV
STCPU
0
RSVD1
SLOCK
RSVD1
STSIM
STEXT
RESET:
0
1
0
U
0
32 XFC CONN
* MAINTAIN LOW LEAKAGE ON THE XFC NODE.
0.01
F
0.1
F
XFC*
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F
C4
C3
C1
VDDSYN
VSSI
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sys
4f
ref Y1
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2f
sys if X = 1
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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