- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69025 > MC68CK338CPV14B1 (FREESCALE SEMICONDUCTOR INC) 32-BIT, 14.4 MHz, MICROCONTROLLER, PQFP144 PDF資料下載
參數(shù)資料
| 型號(hào)： | MC68CK338CPV14B1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 14.4 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁(yè)數(shù)： | 45/133頁(yè) |
| 文件大小： | 944K |
| 代理商： | MC68CK338CPV14B1 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)當(dāng)前第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)
MC68CK338
MOTOROLA
MC68CK338TS/D
19
When the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the upper
byte of SYNCR. Bits in the lower byte show the status of or control the operation of internal and external
clocks. SYNCR can be read or written only when the CPU is operating in supervisor mode.
W — Frequency Control (VCO)
This bit controls a prescaler tap in the synthesizer feedback loop. Setting it increases the VCO speed
by a factor of four. VCO relock delay is required.
X — Frequency Control (Prescaler)
This bit controls a divide by two prescaler that is not in the synthesizer feedback loop. Setting it doubles
the clock speed without changing the VCO speed. No VCO relock delay is required.
Y[5:0] — Frequency Control (Counter)
The Y field controls the modulus down counter in the synthesizer feedback loop, causing it to divide by
a value of Y + 1. Values range from 0 to 63. VCO relock delay is required.
EDIV — E Clock Divide Rate
0 = ECLK frequency is system clock divided by 8.
1 = ECLK frequency is system clock divided by 16.
ECLK is an external M6800 bus clock available on pin ADDR23. Refer to 3.6 Chip-Selects for more
information.
STCPU — Stop CPU32L Clock on LPSTOP
0 = When LPSTOP is executed, the intermodule bus clock (IMBCLK) is held low. When a trace,
reset exception, or SIML interrupt occurs, the IMBCLK turns back on and the CPU32L begins
executing instructions again.
1 = When LPSTOP is executed, the IMBCLK continues to run but is gated off and held low only
where it enters the CPU32L. When a trace, reset exception, or interrupt from any module oc-
curs, the IMBCLK is gated back on where it enters the CPU32L, and execution begins again.
SLOCK — Synthesizer Lock Flag
0 = VCO has not locked, but is enabled on the desired frequency.
1 = VCO has locked on the desired frequency, or is disabled.
The MCU remains in reset until the synthesizer locks, but SLOCK does not indicate synthesizer lock
status until after the user writes to SYNCR.
STSIM — Stop Mode SIML Clock
0 = When LPSTOP is executed, the SIML clock is driven by the crystal oscillator and the VCO is
turned off to conserve power.
1 = When LPSTOP is executed, the SIML clock is driven by the VCO.
STEXT — Stop Mode External Clock
0 = When LPSTOP is executed, the CLKOUT signal is held negated to conserve power.
1 = When LPSTOP is executed, the CLKOUT signal is driven by the SIML clock, as determined by
the state of the STSIM bit.
3.3.4 External MC6800 Bus Clock
The state of the ECLK division rate bit (EDIV) in SYNCR determines clock rate for the ECLK signal avail-
able on pin ADDR23. ECLK is a bus clock for MC6800 devices and peripherals. ECLK frequency can
be set to system clock frequency divided by eight or system clock frequency divided by sixteen. The
clock is enabled by the CS10 field in chip-select pin assignment register 1 (CSPAR1). ECLK operation
during low-power stop is described in the following paragraph. Refer to 3.6 Chip-Selects for more in-
formation about the external bus clock.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68CK338CPV14 | 32-BIT, 14.4 MHz, MICROCONTROLLER, PQFP144 |
| MC68EN360CRC25 | 32-BIT, 25 MHz, RISC MICROCONTROLLER, CPGA241 |
| MC68F333FE | 32-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, CQFP160 |
| MC68F333FC | 32-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP160 |
| MC68HC000L12F | 16-BIT, 16.67 MHz, MICROPROCESSOR, CDIP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68CM16Z1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series |
| MC68CM16Z1CFC16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series |
| MC68CM16Z1CPV16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series |
| MC68E360VR25VLR2 | 功能描述:微處理器 - MPU QUICC ETHRN RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68E360ZP25VLR2 | 功能描述:IC MPU QUICC 32BIT 357-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點(diǎn):- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA（29x29） 包裝:托盤 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。