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| 型號： | MC68CK338CPV14B1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 14.4 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 117/133頁 |
| 文件大小： | 944K |
| 代理商： | MC68CK338CPV14B1 |
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MOTOROLA
MC68CK338
84
MC68CK338TS/D
The time base buses are precharge/discharge type buses with wired-OR capability, so that no hardware
damage occurs when several counters are driving the same bus at the same time.
6.4 Bus Interface Unit Submodule (BIUSM)
The BIUSM connects the SMB to the IMB and allows the CTM6 submodules to communicate with the
CPU. The BIUSM also communicates interrupt requests from the CTM6 submodules to the IMB, and
transfers the interrupt level, arbitration bit and vector number to the CPU during the interrupt acknowl-
edge cycle.
6.4.1 BIUSM Registers
The BIUSM contains a module configuration register, a time base register, and a test register. The
BIUSM register block always occupies the first four register locations in the CTM6 register space and
cannot be relocated within the CTM6 structure. All unused bits and reserved address locations return
zero when read by the software. Writing to unused bits and reserved address locations has no effect.
STOP — Stop Enable
The STOP bit, while asserted, completely stops operation of the CTM6. The BIUSM continues to oper-
ate to allow the CPU access to submodule registers. The CTM6 remains stopped until reset or until the
STOP bit is negated by the CPU.
0 = Allows operation of the CTM6
1 = Stops operation of the CTM6
FRZ — FREEZE Assertion Response
0 = Ignore IMB FREEZE signal
1 = CTM6 stops when IMB FREEZE signal is asserted
NOTE
Some submodules may validate this signal with internal enable bits.
Bit 13 — Not Implemented
VECT[7:6] — Interrupt Vector Base Number Field
This bit field selects the interrupt vector base number for the CTM6. Of the eight bits necessary for vec-
tor number definition, the six least significant bits are programmed by hardware on a submodule basis,
while the two remaining bits are provided by VECT[7:6]. This places the CTM6 vectors in one of four
possible positions in the interrupt vector table. Refer to Table 47.
BIUMCR — BIU Module Configuration Register
$YFF400
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STOP
FRZ
0
VECT[7:6]
IARB[2:0]
0
TBRS1
0
TBRS0
RESET:
0
1
0
Table 47 Interrupt Vector Base Number Bit Field
VECT7
VECT6
Resulting Vector
Base Number
0
$00
0
1
$40
1
0
$80
1
$C0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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