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參數(shù)資料
| 型號： | MC68CK338CPV14B1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 14.4 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 70/133頁 |
| 文件大?。?/td> | 944K |
| 代理商： | MC68CK338CPV14B1 |
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MC68CK338
MOTOROLA
MC68CK338TS/D
41
Data bus pin 9 controls the state of this register following reset. If DATA9 is set to one during reset, the
register is set to $FF, which defines all port F pins as interrupt request inputs. If DATA9 is cleared to
zero during reset, this register is set to $00, defining all port F pins as I/O pins.
3.8 Resets
Reset procedures handle system initialization and recovery from catastrophic failure. The MCU per-
forms resets with a combination of hardware and software. The SIML determines whether a reset is val-
id, asserts control signals, performs basic system configuration based on hardware mode-select inputs,
then passes control to the CPU.
Reset occurs when an active low logic level on the RESET pin is clocked into the SIML. Resets are gat-
ed by the CLKOUT signal. Asynchronous resets are assumed to be catastrophic. An asynchronous re-
set can occur on any clock edge. Synchronous resets are timed to occur at the end of bus cycles. If
there is no clock when RESET is asserted, reset does not occur until the clock starts. Resets are
clocked in order to allow completion of write cycles in progress at the time RESET is asserted.
Reset is the highest-priority CPU32L exception. Any processing in progress is aborted by the reset ex-
ception, and cannot be restarted. Only essential tasks are performed during reset exception processing.
Other initialization tasks must be accomplished by the exception handler routine.
3.8.1 SIML Reset Mode Selection
The logic states of certain data bus pins during reset determine SIML operating configuration. In addi-
tion, the state of the MODCLK pin determines system clock source and the state of the BKPT pin de-
termines what happens during subsequent breakpoint assertions. Table 31 is a summary of reset mode
selection options.
Table 30 Port F Pin Assignments
PFPAR Field
Port F Signal
Alternate Signal
PFPA7
PF7
IRQ7
PFPA6
PF6
IRQ6
PFPA5
PF5
IRQ5
PFPA4
PF4
IRQ4
PFPA3
PF3
IRQ3
PFPA2
PF2
IRQ2
PFPA1
PF1
IRQ1
PFPA0
PF0
MODCLK
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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