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| 型號： | MC68CK338CPV14B1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 14.4 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 118/133頁 |
| 文件大小： | 944K |
| 代理商： | MC68CK338CPV14B1 |
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MC68CK338
MOTOROLA
MC68CK338TS/D
85
IARB[2:0] — Interrupt Arbitration Field
This bit field and the IARB3 bit within each submodule provide 15 different interrupt arbitration numbers
that can be used to arbitrate between interrupt requests occurring on the IMB with the same interrupt
priority level.
The IARB field defaults to zero on reset, preventing the module from arbitrating during an IACK cycle.
If no arbitration takes place during the IACK cycle, the SIML generates a spurious interrupt, indicating
to the system that the interrupt arbitration number has not been initialized.
The CTM6 allows two different arbitration numbers to be used by providing each submodule with its own
IARB3 bit (which can be set or cleared in software). Once IARB[2:0] are assigned in the BIUSM, they
apply to all CTM6 interrupt requests. Therefore, CTM6 submodule interrupts can be prioritized with re-
quests from other modules at the same interrupt level. IARB[2:0] are cleared by reset.
Bits[7:6], [4:1] — Not Implemented
TBRS1, TBRS0 — Time Base Register Bus Select Bits
These bits specify which time base bus is accessed when the time base register (BIUTBR) is read. Re-
fer to Table 48.
BIUTEST — BIUSM Test Register
$YFF402
BIUTEST is used during factory testing of the CTM6. Accesses to BIUTEST must be made while the
MCU is in test mode.
BIUTBR is a read-only register used to read the value present on one of the time base buses. The time
base bus being accessed is determined by TBRS1 and TBRS0 in BIUMCR. Writing to BIUTBR has no
effect during normal operation.
6.5 Counter Prescaler Submodule (CPSM)
The counter prescaler submodule (CPSM) is a programmable divider system that provides the CTM6
counters with a choice of six clock signals (PCLKx) derived from the sixth frequency MCU system clock
(fsys). Five of these frequencies are derived from a fixed divider chain. The divide ratio is software se-
lectable from a choice of four divide ratios.
The CPSM is contained within the BIUSM. Figure 19 shows a block diagram of the CPSM.
Table 48 Time Base Register Bus Select Bits
TBRS1
TBRS0
Time Base Bus
0
TBB1
0
1
TBB2
1
0
TBB3
1
TBB4
BIUTBR — BIUSM Time Base Register
$YFF404
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14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET:
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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