參數(shù)資料
型號(hào)： MC145225
廠商： Motorola, Inc.
英文描述： Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器)
中文描述： 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器）
文件頁數(shù)： 6/71頁
文件大?。?/td> 906K
代理商： MC145225
MC145225 MC145230
6
MOTOROLA RF/IF DEVICE DATA
3E. DAC CHARACTERISTICS
Vpos = 1.8 to 3.6 V, DAC Vpos = 1.8 to 3.6 V; TA = –40 to 85
°
C
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Parameter
Condition
130
Guaranteed
Limit
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Unit
Resolution
No External Load
8
Bits
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Maximum Integral Nonlinearity
±
1
LSB
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Maximum Offset Voltage from Gnd
1
LSB
Maximum Offset Voltage from DAC Vpos
Maximum Output Impedance
No External Load
2
LSB
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Over Entire Output Range, Including Zero
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á
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k
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3F. VOLTAGE MULTIPLIER AND KEEP–ALIVE OSCILLATOR CHARACTERISTICS
Voltages Referenced to Gnd, TA = –40 to 85
°
C
Parameter
Condition
Guaranteed
Limit
Unit
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á
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Vpos = 3.6 V
Sourcing, Measured at Cmult pin
Vpos = 1.8 V
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4.75 to 5.35
á
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3G. DYNAMIC CHARACTERISTICS OF DIGITAL PINS
Vpos = 1.8 to 3.6 V, TA = –40 to 85
°
C, Input tr = tf = 10 ns, CL = 25 pF
Parameter
Figure
No.
Symbol
Guaranteed
Limit
Unit
Serial Data Clk Frequency
NOTE: Refer to Clk tw Below
1
fclk
dc to 10
MHz
Maximum Propagation Delay, Enb to Output A (Selected as General–Purpose Output)
2, 7
tPLH, tPHL
tPLH, tPHL,
tPZL, tPLZ,
tPZH, tPHZ
200
ns
Maximum Propagation Delay, Enb to Output B
2, 3, 7, 8
200
ns
Maximum Propagation Delay, Enb to Output C
4, 8
tPZL, tPLZ
tTLH, tTHL
tsu, th
tsu, th, trec
tw
tw
Cin
200
ns
Maximum Output Transition Time, Output A; Output B with Active Pullup and Pulldown
2, 7
75
ns
Minimum Setup and Hold Times, Din versus Clk
Minimum Setup, Hold, and Recovery Times, Enb versus Clk
5
30
ns
6
100
ns
Minimum Pulse Width, Inactive (High) Time, Enb
6
*
cycles
Minimum Pulse Width, Clk
1
50
ns
Maximum Input Capacitance — Din, CLK, Enb
10
pF
*For Hr register access, the minimum limit is 20 Osce cycles.
For Hn register access, the minimum limit is 27 fin cycles.
For N register access, the minimum limit is 20 Osce cycles + 99 fin cycles.
When the timer is used for adapt, the minimum limit after the second N register access and before the next register access is the time–out interval + 99 fin cycles.
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