參數(shù)資料
型號(hào)： MC145225
廠商： Motorola, Inc.
英文描述： Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器)
中文描述： 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器）
文件頁數(shù)： 41/71頁
文件大?。?/td> 906K
代理商： MC145225
MC145225 MC145230
41
MOTOROLA RF/IF DEVICE DATA
7C. MAIN LOOP FILTER DESIGN — ADAPT
Introduction
For PSpice simulation, the schematic model shown in
Figure 41 was chosen. The classical PLL model employing a
phase–frequency detector, a VCO, and an adaptive loop filter
is used to simplify visualization of circuit operation. The
parameter tables allow for modification of circuit performance
by providing an easy method for altering critical values
without necessitating changes to sub–level schematics. The
definition for the terms are:
tw = 2
π
,
fr = reference frequency,
td = time delay; allows delay of the start of the high
current mode (used to perform reference spur
measurements),
CPL = charge pump low current,
CPH = charge pump high current,
N = N counter value,
Sz = amount the N counter is being increased (or
decreased) by,
St = number of fr cycles that CPH is active; this value
is either 16, 32, 64, or 128,
VCPHH = charge pump voltage – high,
VCPHL = charge pump voltage – low,
K1 = VCO gain (Hz/volt),
fc = VCO frequency at 0 V control voltage,
H = reference spur scaling factor.
Modeling the Phase–frequency Detector
Figure 42 is a schematic of the phase–frequency detector.
It includes the reference oscillator model, phase–frequency
detector model, and charge pump models. V1 is the control
element used to generate the step time for switching between
CPL and CPH. The signal source VPULSE, is used to
simulate the timer that controls when CPL and CPH are
turned on. PW calculates the pulse width that simulates the
counter from the values for St and fr that are entered in the
parameter tables on the top level schematic.
Figure 41. Top Level PLL Model
50 p
PDout–Lo
In
HB2
C2
20 k
C5
C6
1 k
R10
ctrl
330 p
C4
Out
VCO
HB1
33 p
R3
Parameters:
tw
fr
H
Parameters:
N
Sz
St
6.283185308
25 k
1
Parameters:
CPL
CPH
K1
1 x 10–3
4 x 10–3
4 x 106
29320
400
32
PDout–Hi
+
+
60.4 k
R1
C1
40.2 k
+
+
3300 p
10%
330 p
fr N – fc
C3
330 p
fr N – fc
R2
Parameters:
VCPHH
VCPHL
fc
5
0
727.6 x 106
Parameters:
td
0
K1
IC =
fr N – fc
K1
IC =
fr N – fc
K1
IC =
K1
IC =
0
0
0
0
Figure 42. Phase–frequency Detector with Dual Charge Pumps
HB1
Shift
+
–
HB3
HB2
PDout–Lo
PDout–Hi
PDout–Hi
Shift
PDout–Lo
R
φ
V
φ
R
φ
V
φ
fin
Ref
Ref
Shift
V1
In
PW =4 fr
St
td =
fr
4 td
0
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