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參數(shù)資料
| 型號： | MC145225 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器) |
| 中文描述： | 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 40/71頁 |
| 文件大?。?/td> | 906K |
| 代理商： | MC145225 |
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MC145225 MC145230
40
MOTOROLA RF/IF DEVICE DATA
The equation for the sine generator is:
N
fc time + v(int) .
e = sin tw
fc is defined as the output frequency when the control voltage
is 0. This is the expected VCO frequency before frequency
division. For the purpose of simulation, the counter value, N,
has been written into the equation to ensure the correlation
between the modeled circuit and the mathematical loop filter
calculations. tw is 2
π
; additional decimal places can be added
as needed. v(int) is the control voltage effect and is defined in
these examples as:
k1
v(cntl) 1 x 10–6 .
v(int) =
twN
where k1 is the VCO gain in rad/V.
The value C1 in the schematic of the VCO can be
arbitrarily changed; however, the value must match that of
Qc. Qc determines the value of the current to be integrated by
the capacitor C1. R1 is arbitrarily set to 1 x 1099 and is not an
active part of the circuit; however, it must be included to
prevent open pin errors from the PSpice software. The
GVALUE function is used to perform the generation of v(int).
There is some interaction between the integrator, (GVALUE
output and C1) and R1. V(int) is a continuous ramp that is
loaded by the resistance of R1. Unless the GVALUE output
current is sufficiently large for the value chosen for R1, the
VCO control voltage required to maintain lock will increase
throughout the simulation producing nonlinear operation.
Modifications to the circuit can be performed either by
changing the values in the parameter list or for major
changes to the VCO characteristics, the equations for the
sine generator, or control voltage can be altered.
The output of the sine generator is amplified by 1000 to
produce a sharp rise/fall time and the output limited to swing
between the values of 0 V and 5 V to convert it to a digital
output. The resultant circuit/symbol accepts a voltage input
from the loop filter and produces a square wave output at the
desired frequency. This frequency should be chosen to
represent the frequency present at the output of the N
counter of the PLL frequency synthesizer.
The second output represented by the ABM function is a
sine wave output of the frequency expected from the actual
VCO. The primary purpose of this output is to allow full
frequency simulation for spectrum analysis. By running a
transient analysis of sufficient time, it is possible to determine
spur content and level. If sufficient resolution is used in the
simulation, the PSpice probe FFT transform can be used to
provide the typical spectrum analyzer display.
Loop Filter Simulation
The circuit shown in Figure 40 is used to simulate the
closed loop operation for a single charge pump output.
Component values for the loop filter should be computed
using information from the previous section. Initial conditions
can be set using the “IC1” symbol with starting values
specifying the initial condition.
By adjusting component values for the loop filter,
performance of the closed loop operation can be monitored.
The control voltage to the input of the VCO can be monitored
for a variety of conditions including settling time, lock time,
and ripple present at the VCO input. In addition, the output of
the VCO can be monitored for spur sidebands caused by
ripple on the loop filter output; however, expected operation
at high frequencies may be difficult due to the excessive data
that can be generated.
As the divider ratio, N, increases for a fixed step
frequency, the number of data points required to obtain
sufficient information to overcome aliasing problems may
become excessively large. In addition, the number of
samples required should be three or more per cycle. For
VCO frequencies in the range of 500 MHz, this means the
step ceiling needs to be in the range of 100 to 500 ps. If a
simulation time of 1 ms is needed, the actual computer time
can be several hours with data accumulation in the 1– to
2–Gbyte range.
Figure 40. PLL Closed Loop Model
U3
Ref
In
HB2
R3
75 k
C2
C3
1 k
R4
ctrl
+
–
+
+
IC = 3.5
0.1 n
C1
V1
Out
VCOout
7.5 k
IC = 3.5
PDout
R
φ
HB1
V
φ
R
φ
V
φ
0.2 n
2 n
R1
0
0
0
0
0
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