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參數(shù)資料
| 型號： | MC145225 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器) |
| 中文描述： | 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 42/71頁 |
| 文件大?。?/td> | 906K |
| 代理商： | MC145225 |
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MC145225 MC145230
42
MOTOROLA RF/IF DEVICE DATA
Reference Oscillator
The reference oscillator is shown in Figure 43. The
oscillator is modeled using an analog behavioral block. The
function for the block is written as an “If” condition. If the
signal shift is low, the reference frequency fr will be generated
if shift is high, a signal of four times fr will be generated. The
limiter/gain block converts the low level sine wave output of
the analog behavioral block into a square wave. The values
of 0 for the low value and 5 for the high value are used
throughout. These values are chosen out of habit and are not
critical in an analog behavioral environment, providing the
conformity is universal throughout the design.
Figure 43. Reference Oscillator
If [V(shift) < 1, sin (tw fr time), sin (tw fr time) 4]
Shift
5 V
0 V
1 k
Ref
Shift
Phase–frequency Detector
The actual phase–frequency detector model minus
reference oscillator and charge pumps is shown in Figure 44.
The detector is composed of three delay modules: a
behavioral AND gate, and two RS flip–flops. The STP
function resets the phase/frequency detector logic on
initiation of the simulator. The circuit for the behavioral RS
flip–flop is shown in Figure 45.
The RS flip–flop equation illustrates the benefit of using
the behavioral block instead of using a primitive logic
element. A delay block and the behavioral gate equation
generate a pulse whose width is equal to the value of the
delay block. To generate the output using a primitive logic
element such as a NAND gate, an inverter would be
necessary to invert one of the NAND inputs. This approach
requires three elements to be used instead of the two of the
behavioral approach just for the pulse generator. In the
behavioral approach, the equation for the behavioral AND
gate is folded into the RS flip–flop, eliminating a separate
gate altogether. Constructing the model with classic logic
elements would require two NOR gates for the flip–flop, a
delay element, an inverter, and an AND gate; five elements
as compared with three for the behavioral approach. Since
the RS flip–flop is used in two places in the model, four less
components are needed for simulation. Since the speed of
the simulation is directly impacted by the number of
components being simulated, any reduction in the total
number of components is a savings in simulation time and
computer memory.
The RS flip–flops generate the lead or lag outputs that are
used to “steer” the VCO. The pulse generator equation
produces narrow pulses coincident with the leading edge of
each of the input signals. These pulses set the appropriate
RS flip–flop. Once set, the leading flip–flop must wait until the
lagging flip–flop is also set. The behavioral AND gate
provides the necessary output pulse to reset the flip–flops.
The delay element placed at the output of the behavioral
AND gate prevents an undefined state for the detector. The
value 5 ns is chosen to correspond with the data sheet. The
logic functions as a three state phase/frequency detector with
an operating range of
±
2
π
. R
φ
and V
φ
deliver positive pulses,
whose width represents the amount of the lead of each input
over the other input.
Figure 44. Phase–frequency Detector Logic
Q1
HB1
Ref
In
In2
In1
Qout
R
φ
V
φ
Delay
5 ns
Q2
In2
In1
Qout
HB2
If [V(Q1)>=1 & V(Q2)>=1 | V(delay)>=1, 5, 0]
5 STP (5 ns – Time)
Delay
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